o: ActiveSupport::Cache::Entry :@compressedF: @value"X_"Q_
Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_VIO_FreqSel.xco
1 
##############################################################
2 
#
3 
# Xilinx Core Generator version 14.5
4 
# Date: Thu Jun 20 12:56:15 2013
5 
#
6 
##############################################################
7 
#
8 
#  This file contains the customisation parameters for a
9 
#  Xilinx CORE Generator IP GUI. It is strongly recommended
10 
#  that you do not manually alter this file as it may cause
11 
#  unexpected and unsupported behavior.
12 
#
13 
##############################################################
14 
#
15 
#  Generated from component: xilinx.com:ip:chipscope_vio:1.05.a
16 
#
17 
##############################################################
18 
#
19 
# BEGIN Project Options
20 
SET addpads = false
21 
SET asysymbol = true
22 
SET busformat = BusFormatAngleBracketNotRipped
23 
SET createndf = false
24 
SET designentry = VHDL
25 
SET device = xc3s50an
26 
SET devicefamily = spartan3a
27 
SET flowvendor = Other
28 
SET formalverification = false
29 
SET foundationsym = false
30 
SET implementationfiletype = Ngc
31 
SET package = tqg144
32 
SET removerpms = false
33 
SET simulationfiles = Behavioral
34 
SET speedgrade = -4
35 
SET verilogsim = false
36 
SET vhdlsim = true
37 
# END Project Options
38 
# BEGIN Select
39 
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
40 
# END Select
41 
# BEGIN Parameters
42 
CSET asynchronous_input_port_width=8
43 
CSET asynchronous_output_port_width=8
44 
CSET component_name=ChipScope_VIO_FreqSel
45 
CSET constraint_type=external
46 
CSET enable_asynchronous_input_port=false
47 
CSET enable_asynchronous_output_port=false
48 
CSET enable_synchronous_input_port=true
49 
CSET enable_synchronous_output_port=true
50 
CSET example_design=false
51 
CSET invert_clock_input=false
52 
CSET synchronous_input_port_width=8
53 
CSET synchronous_output_port_width=8
54 
# END Parameters
55 
# BEGIN Extra information
56 
MISC pkg_timestamp=2013-03-26T22:44:59Z
57 
# END Extra information
58 
GENERATE
59 
# CRC: c6d481e1
Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ILA_18_1024.xco
1 
##############################################################
2 
#
3 
# Xilinx Core Generator version 14.5
4 
# Date: Thu Jun 20 12:43:44 2013
5 
#
6 
##############################################################
7 
#
8 
#  This file contains the customisation parameters for a
9 
#  Xilinx CORE Generator IP GUI. It is strongly recommended
10 
#  that you do not manually alter this file as it may cause
11 
#  unexpected and unsupported behavior.
12 
#
13 
##############################################################
14 
#
15 
#  Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
16 
#
17 
##############################################################
18 
#
19 
# BEGIN Project Options
20 
SET addpads = false
21 
SET asysymbol = true
22 
SET busformat = BusFormatAngleBracketNotRipped
23 
SET createndf = false
24 
SET designentry = VHDL
25 
SET device = xc3s50an
26 
SET devicefamily = spartan3a
27 
SET flowvendor = Other
28 
SET formalverification = false
29 
SET foundationsym = false
30 
SET implementationfiletype = Ngc
31 
SET package = tqg144
32 
SET removerpms = false
33 
SET simulationfiles = Behavioral
34 
SET speedgrade = -4
35 
SET verilogsim = false
36 
SET vhdlsim = true
37 
# END Project Options
38 
# BEGIN Select
39 
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
40 
# END Select
41 
# BEGIN Parameters
42 
CSET check_bramcount=false
43 
CSET component_name=ChipScope_ILA_18_1024
44 
CSET constraint_type=external
45 
CSET counter_width_1=4
46 
CSET counter_width_10=Disabled
47 
CSET counter_width_11=Disabled
48 
CSET counter_width_12=Disabled
49 
CSET counter_width_13=Disabled
50 
CSET counter_width_14=Disabled
51 
CSET counter_width_15=Disabled
52 
CSET counter_width_16=Disabled
53 
CSET counter_width_2=Disabled
54 
CSET counter_width_3=Disabled
55 
CSET counter_width_4=Disabled
56 
CSET counter_width_5=Disabled
57 
CSET counter_width_6=Disabled
58 
CSET counter_width_7=Disabled
59 
CSET counter_width_8=Disabled
60 
CSET counter_width_9=Disabled
61 
CSET data_port_width=18
62 
CSET data_same_as_trigger=false
63 
CSET disable_save_keep=false
64 
CSET enable_storage_qualification=true
65 
CSET enable_trigger_output_port=true
66 
CSET example_design=false
67 
CSET exclude_from_data_storage_1=true
68 
CSET exclude_from_data_storage_10=true
69 
CSET exclude_from_data_storage_11=true
70 
CSET exclude_from_data_storage_12=true
71 
CSET exclude_from_data_storage_13=true
72 
CSET exclude_from_data_storage_14=true
73 
CSET exclude_from_data_storage_15=true
74 
CSET exclude_from_data_storage_16=true
75 
CSET exclude_from_data_storage_2=true
76 
CSET exclude_from_data_storage_3=true
77 
CSET exclude_from_data_storage_4=true
78 
CSET exclude_from_data_storage_5=true
79 
CSET exclude_from_data_storage_6=true
80 
CSET exclude_from_data_storage_7=true
81 
CSET exclude_from_data_storage_8=true
82 
CSET exclude_from_data_storage_9=true
83 
CSET match_type_1=basic_with_edges
84 
CSET match_type_10=basic_with_edges
85 
CSET match_type_11=basic_with_edges
86 
CSET match_type_12=basic_with_edges
87 
CSET match_type_13=basic_with_edges
88 
CSET match_type_14=basic_with_edges
89 
CSET match_type_15=basic_with_edges
90 
CSET match_type_16=basic_with_edges
91 
CSET match_type_2=basic_with_edges
92 
CSET match_type_3=basic_with_edges
93 
CSET match_type_4=basic_with_edges
94 
CSET match_type_5=basic_with_edges
95 
CSET match_type_6=basic_with_edges
96 
CSET match_type_7=basic_with_edges
97 
CSET match_type_8=basic_with_edges
98 
CSET match_type_9=basic_with_edges
99 
CSET match_units_1=3
100 
CSET match_units_10=1
101 
CSET match_units_11=1
102 
CSET match_units_12=1
103 
CSET match_units_13=1
104 
CSET match_units_14=1
105 
CSET match_units_15=1
106 
CSET match_units_16=1
107 
CSET match_units_2=1
108 
CSET match_units_3=1
109 
CSET match_units_4=1
110 
CSET match_units_5=1
111 
CSET match_units_6=1
112 
CSET match_units_7=1
113 
CSET match_units_8=1
114 
CSET match_units_9=1
115 
CSET max_sequence_levels=16
116 
CSET number_of_trigger_ports=1
117 
CSET sample_data_depth=1024
118 
CSET sample_on=Rising
119 
CSET trigger_port_width_1=24
120 
CSET trigger_port_width_10=8
121 
CSET trigger_port_width_11=8
122 
CSET trigger_port_width_12=8
123 
CSET trigger_port_width_13=8
124 
CSET trigger_port_width_14=8
125 
CSET trigger_port_width_15=8
126 
CSET trigger_port_width_16=8
127 
CSET trigger_port_width_2=8
128 
CSET trigger_port_width_3=8
129 
CSET trigger_port_width_4=8
130 
CSET trigger_port_width_5=8
131 
CSET trigger_port_width_6=8
132 
CSET trigger_port_width_7=8
133 
CSET trigger_port_width_8=8
134 
CSET trigger_port_width_9=8
135 
CSET use_rpms=true
136 
# END Parameters
137 
# BEGIN Extra information
138 
MISC pkg_timestamp=2013-03-26T22:44:34Z
139 
# END Extra information
140 
GENERATE
141 
# CRC: ab76e1ca
Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_VIO_UserOut.xco
1 
##############################################################
2 
#
3 
# Xilinx Core Generator version 14.5
4 
# Date: Thu Jun 20 12:55:33 2013
5 
#
6 
##############################################################
7 
#
8 
#  This file contains the customisation parameters for a
9 
#  Xilinx CORE Generator IP GUI. It is strongly recommended
10 
#  that you do not manually alter this file as it may cause
11 
#  unexpected and unsupported behavior.
12 
#
13 
##############################################################
14 
#
15 
#  Generated from component: xilinx.com:ip:chipscope_vio:1.05.a
16 
#
17 
##############################################################
18 
#
19 
# BEGIN Project Options
20 
SET addpads = false
21 
SET asysymbol = true
22 
SET busformat = BusFormatAngleBracketNotRipped
23 
SET createndf = false
24 
SET designentry = VHDL
25 
SET device = xc3s50an
26 
SET devicefamily = spartan3a
27 
SET flowvendor = Other
28 
SET formalverification = false
29 
SET foundationsym = false
30 
SET implementationfiletype = Ngc
31 
SET package = tqg144
32 
SET removerpms = false
33 
SET simulationfiles = Behavioral
34 
SET speedgrade = -4
35 
SET verilogsim = false
36 
SET vhdlsim = true
37 
# END Project Options
38 
# BEGIN Select
39 
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
40 
# END Select
41 
# BEGIN Parameters
42 
CSET asynchronous_input_port_width=8
43 
CSET asynchronous_output_port_width=8
44 
CSET component_name=ChipScope_VIO_UserOut
45 
CSET constraint_type=external
46 
CSET enable_asynchronous_input_port=false
47 
CSET enable_asynchronous_output_port=false
48 
CSET enable_synchronous_input_port=false
49 
CSET enable_synchronous_output_port=true
50 
CSET example_design=false
51 
CSET invert_clock_input=false
52 
CSET synchronous_input_port_width=8
53 
CSET synchronous_output_port_width=3
54 
# END Parameters
55 
# BEGIN Extra information
56 
MISC pkg_timestamp=2013-03-26T22:44:59Z
57 
# END Extra information
58 
GENERATE
59 
# CRC: 738ddf25
Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/coregen.cgp
1 
SET busformat = BusFormatAngleBracketNotRipped
2 
SET designentry = VHDL
3 
SET device = xc3s50an
4 
SET devicefamily = spartan3a
5 
SET flowvendor = Other
6 
SET package = tqg144
7 
SET speedgrade = -4
8 
SET verilogsim = false
9 
SET vhdlsim = true
Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/!____!.txt
1 
CoreGenerator Project Files
2 
---------------------------
3 

  		




  
  4
  
    
Software:	ISE 14.5 (WebPack)


  		




  
  5
  
    
Device:		Spartan3AN XC3S50AN-4TQG144C


  		




  
  6
  
    

  		




  
  7
  
    

  		




  
  8
  
    
Input (source) Files


  		




  
  9
  
    
--------------------


  		




  
  10
  
    

  		




  
  11
  
    
S3AN01_ChipScopeILA.cgp		- Core Generator Project File (used by GUI CoreGen)


  		




  
  12
  
    

  		




  
  13
  
    
ChipScope_ICON.xco		- ChipScope Config Block Configuration File


  		




  
  14
  
    
ChipScope_ILA_18_1024.xco	- ChipScope Integrated Logic Analyser Configuration File 18 bits 1024 smaples


  		




  
  15
  
    
ChipScope_ILA_9_2048.xco	- ChipScope Integrated Logic Analyser Configuration File 9 bits 2048 smaples


  		




  
  16
  
    
ChipScope_VIO_FreqSel.xco	- ChipScope Virtul IO Configuration File (used for Frequency Selection)


  		




  
  17
  
    
ChipScope_VIO_UserOut.xco	- ChipScope Virtul IO Configuration File (used for User Output)


  		




  
  18
  
    

  		




  
  19
  
    
All other files may be deleted. Open .cgp file in CoreGenerator and let it regenerate


  		




  
  20
  
    
all cores.


  		












  

    
      Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ICON.xco
    
  





  
  1
  
    
##############################################################


  		




  
  2
  
    
#


  		




  
  3
  
    
# Xilinx Core Generator version 14.5


  		




  
  4
  
    
# Date: Thu Jun 20 12:54:35 2013


  		




  
  5
  
    
#


  		




  
  6
  
    
##############################################################


  		




  
  7
  
    
#


  		




  
  8
  
    
#  This file contains the customisation parameters for a


  		




  
  9
  
    
#  Xilinx CORE Generator IP GUI. It is strongly recommended


  		




  
  10
  
    
#  that you do not manually alter this file as it may cause


  		




  
  11
  
    
#  unexpected and unsupported behavior.


  		




  
  12
  
    
#


  		




  
  13
  
    
##############################################################


  		




  
  14
  
    
#


  		




  
  15
  
    
#  Generated from component: xilinx.com:ip:chipscope_icon:1.06.a


  		




  
  16
  
    
#


  		




  
  17
  
    
##############################################################


  		




  
  18
  
    
#


  		




  
  19
  
    
# BEGIN Project Options


  		




  
  20
  
    
SET addpads = false


  		




  
  21
  
    
SET asysymbol = true


  		




  
  22
  
    
SET busformat = BusFormatAngleBracketNotRipped


  		




  
  23
  
    
SET createndf = false


  		




  
  24
  
    
SET designentry = VHDL


  		




  
  25
  
    
SET device = xc3s50an


  		




  
  26
  
    
SET devicefamily = spartan3a


  		




  
  27
  
    
SET flowvendor = Other


  		




  
  28
  
    
SET formalverification = false


  		




  
  29
  
    
SET foundationsym = false


  		




  
  30
  
    
SET implementationfiletype = Ngc


  		




  
  31
  
    
SET package = tqg144


  		




  
  32
  
    
SET removerpms = false


  		




  
  33
  
    
SET simulationfiles = Behavioral


  		




  
  34
  
    
SET speedgrade = -4


  		




  
  35
  
    
SET verilogsim = false


  		




  
  36
  
    
SET vhdlsim = true


  		




  
  37
  
    
# END Project Options


  		




  
  38
  
    
# BEGIN Select


  		




  
  39
  
    
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a


  		




  
  40
  
    
# END Select


  		




  
  41
  
    
# BEGIN Parameters


  		




  
  42
  
    
CSET component_name=ChipScope_ICON


  		




  
  43
  
    
CSET constraint_type=external


  		




  
  44
  
    
CSET enable_jtag_bufg=true


  		




  
  45
  
    
CSET example_design=false


  		




  
  46
  
    
CSET number_control_ports=3


  		




  
  47
  
    
CSET use_ext_bscan=false


  		




  
  48
  
    
CSET use_softbscan=false


  		




  
  49
  
    
CSET use_unused_bscan=false


  		




  
  50
  
    
CSET user_scan_chain=USER1


  		




  
  51
  
    
# END Parameters


  		




  
  52
  
    
# BEGIN Extra information


  		




  
  53
  
    
MISC pkg_timestamp=2013-03-26T22:44:10Z


  		




  
  54
  
    
# END Extra information


  		




  
  55
  
    
GENERATE


  		




  
  56
  
    
# CRC: 1a9afcd1


  		












  

    
      Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ILA_9_2048.xco
    
  





  
  1
  
    
##############################################################


  		




  
  2
  
    
#


  		




  
  3
  
    
# Xilinx Core Generator version 14.5


  		




  
  4
  
    
# Date: Thu Jun 20 13:35:12 2013


  		




  
  5
  
    
#


  		




  
  6
  
    
##############################################################


  		




  
  7
  
    
#


  		




  
  8
  
    
#  This file contains the customisation parameters for a


  		




  
  9
  
    
#  Xilinx CORE Generator IP GUI. It is strongly recommended


  		




  
  10
  
    
#  that you do not manually alter this file as it may cause


  		




  
  11
  
    
#  unexpected and unsupported behavior.


  		




  
  12
  
    
#


  		




  
  13
  
    
##############################################################


  		




  
  14
  
    
#


  		




  
  15
  
    
#  Generated from component: xilinx.com:ip:chipscope_ila:1.05.a


  		




  
  16
  
    
#


  		




  
  17
  
    
##############################################################


  		




  
  18
  
    
#


  		




  
  19
  
    
# BEGIN Project Options


  		




  
  20
  
    
SET addpads = false


  		




  
  21
  
    
SET asysymbol = true


  		




  
  22
  
    
SET busformat = BusFormatAngleBracketNotRipped


  		




  
  23
  
    
SET createndf = false


  		




  
  24
  
    
SET designentry = VHDL


  		




  
  25
  
    
SET device = xc3s50an


  		




  
  26
  
    
SET devicefamily = spartan3a


  		




  
  27
  
    
SET flowvendor = Other


  		




  
  28
  
    
SET formalverification = false


  		




  
  29
  
    
SET foundationsym = false


  		




  
  30
  
    
SET implementationfiletype = Ngc


  		




  
  31
  
    
SET package = tqg144


  		




  
  32
  
    
SET removerpms = false


  		




  
  33
  
    
SET simulationfiles = Behavioral


  		




  
  34
  
    
SET speedgrade = -4


  		




  
  35
  
    
SET verilogsim = false


  		




  
  36
  
    
SET vhdlsim = true


  		




  
  37
  
    
# END Project Options


  		




  
  38
  
    
# BEGIN Select


  		




  
  39
  
    
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a


  		




  
  40
  
    
# END Select


  		




  
  41
  
    
# BEGIN Parameters


  		




  
  42
  
    
CSET check_bramcount=false


  		




  
  43
  
    
CSET component_name=ChipScope_ILA_9_2048


  		




  
  44
  
    
CSET constraint_type=external


  		




  
  45
  
    
CSET counter_width_1=4


  		




  
  46
  
    
CSET counter_width_10=Disabled


  		




  
  47
  
    
CSET counter_width_11=Disabled


  		




  
  48
  
    
CSET counter_width_12=Disabled


  		




  
  49
  
    
CSET counter_width_13=Disabled


  		




  
  50
  
    
CSET counter_width_14=Disabled


  		




  
  51
  
    
CSET counter_width_15=Disabled


  		




  
  52
  
    
CSET counter_width_16=Disabled


  		




  
  53
  
    
CSET counter_width_2=Disabled


  		




  
  54
  
    
CSET counter_width_3=Disabled


  		




  
  55
  
    
CSET counter_width_4=Disabled


  		




  
  56
  
    
CSET counter_width_5=Disabled


  		




  
  57
  
    
CSET counter_width_6=Disabled


  		




  
  58
  
    
CSET counter_width_7=Disabled


  		




  
  59
  
    
CSET counter_width_8=Disabled


  		




  
  60
  
    
CSET counter_width_9=Disabled


  		




  
  61
  
    
CSET data_port_width=9


  		




  
  62
  
    
CSET data_same_as_trigger=false


  		




  
  63
  
    
CSET disable_save_keep=false


  		




  
  64
  
    
CSET enable_storage_qualification=true


  		




  
  65
  
    
CSET enable_trigger_output_port=true


  		




  
  66
  
    
CSET example_design=false


  		




  
  67
  
    
CSET exclude_from_data_storage_1=true


  		




  
  68
  
    
CSET exclude_from_data_storage_10=true


  		




  
  69
  
    
CSET exclude_from_data_storage_11=true


  		




  
  70
  
    
CSET exclude_from_data_storage_12=true


  		




  
  71
  
    
CSET exclude_from_data_storage_13=true


  		




  
  72
  
    
CSET exclude_from_data_storage_14=true


  		




  
  73
  
    
CSET exclude_from_data_storage_15=true


  		




  
  74
  
    
CSET exclude_from_data_storage_16=true


  		




  
  75
  
    
CSET exclude_from_data_storage_2=true


  		




  
  76
  
    
CSET exclude_from_data_storage_3=true


  		




  
  77
  
    
CSET exclude_from_data_storage_4=true


  		




  
  78
  
    
CSET exclude_from_data_storage_5=true


  		




  
  79
  
    
CSET exclude_from_data_storage_6=true


  		




  
  80
  
    
CSET exclude_from_data_storage_7=true


  		




  
  81
  
    
CSET exclude_from_data_storage_8=true


  		




  
  82
  
    
CSET exclude_from_data_storage_9=true


  		




  
  83
  
    
CSET match_type_1=basic_with_edges


  		




  
  84
  
    
CSET match_type_10=basic_with_edges


  		




  
  85
  
    
CSET match_type_11=basic_with_edges


  		




  
  86
  
    
CSET match_type_12=basic_with_edges


  		




  
  87
  
    
CSET match_type_13=basic_with_edges


  		




  
  88
  
    
CSET match_type_14=basic_with_edges


  		




  
  89
  
    
CSET match_type_15=basic_with_edges


  		




  
  90
  
    
CSET match_type_16=basic_with_edges


  		




  
  91
  
    
CSET match_type_2=basic_with_edges


  		




  
  92
  
    
CSET match_type_3=basic_with_edges


  		




  
  93
  
    
CSET match_type_4=basic_with_edges


  		




  
  94
  
    
CSET match_type_5=basic_with_edges


  		




  
  95
  
    
CSET match_type_6=basic_with_edges


  		




  
  96
  
    
CSET match_type_7=basic_with_edges


  		




  
  97
  
    
CSET match_type_8=basic_with_edges


  		




  
  98
  
    
CSET match_type_9=basic_with_edges


  		




  
  99
  
    
CSET match_units_1=3


  		




  
  100
  
    
CSET match_units_10=1


  		




  
  101
  
    
CSET match_units_11=1


  		




  
  102
  
    
CSET match_units_12=1


  		




  
  103
  
    
CSET match_units_13=1


  		




  
  104
  
    
CSET match_units_14=1


  		




  
  105
  
    
CSET match_units_15=1


  		




  
  106
  
    
CSET match_units_16=1


  		




  
  107
  
    
CSET match_units_2=1


  		




  
  108
  
    
CSET match_units_3=1


  		




  
  109
  
    
CSET match_units_4=1


  		




  
  110
  
    
CSET match_units_5=1


  		




  
  111
  
    
CSET match_units_6=1


  		




  
  112
  
    
CSET match_units_7=1


  		




  
  113
  
    
CSET match_units_8=1


  		




  
  114
  
    
CSET match_units_9=1


  		




  
  115
  
    
CSET max_sequence_levels=16


  		




  
  116
  
    
CSET number_of_trigger_ports=1


  		




  
  117
  
    
CSET sample_data_depth=2048


  		




  
  118
  
    
CSET sample_on=Rising


  		




  
  119
  
    
CSET trigger_port_width_1=24


  		




  
  120
  
    
CSET trigger_port_width_10=8


  		




  
  121
  
    
CSET trigger_port_width_11=8


  		




  
  122
  
    
CSET trigger_port_width_12=8


  		




  
  123
  
    
CSET trigger_port_width_13=8


  		




  
  124
  
    
CSET trigger_port_width_14=8


  		




  
  125
  
    
CSET trigger_port_width_15=8


  		




  
  126
  
    
CSET trigger_port_width_16=8


  		




  
  127
  
    
CSET trigger_port_width_2=8


  		




  
  128
  
    
CSET trigger_port_width_3=8


  		




  
  129
  
    
CSET trigger_port_width_4=8


  		




  
  130
  
    
CSET trigger_port_width_5=8


  		




  
  131
  
    
CSET trigger_port_width_6=8


  		




  
  132
  
    
CSET trigger_port_width_7=8


  		




  
  133
  
    
CSET trigger_port_width_8=8


  		




  
  134
  
    
CSET trigger_port_width_9=8


  		




  
  135
  
    
CSET use_rpms=true


  		




  
  136
  
    
# END Parameters


  		




  
  137
  
    
# BEGIN Extra information


  		




  
  138
  
    
MISC pkg_timestamp=2013-03-26T22:44:34Z


  		




  
  139
  
    
# END Extra information


  		




  
  140
  
    
GENERATE


  		




  
  141
  
    
# CRC: 100acb04


  		












  

    
      Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/Version
    
  





  
  1
  
    
TimeStamp:     2013_06_25__09_41


  		




  
  2
  
    
ComputerName:  MIHOMSI


  		




  
  3
  
    
ISE Version:   13.3


  		




  
  4
  
    
ReleaseInfo:   None


  		












  

    
      Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/Version
    
  





  
  1
  
    
TimeStamp:     2013_06_25__17_31


  		




  
  2
  
    
ComputerName:  MIHO-W7


  		




  
  3
  
    
ISE Version:   14.5


  		




  
  4
  
    
ReleaseInfo:   None


  		












  

    
      Modules/CPLD_FPGA/XILINX_CHIPSCOPE/DirInfo.txt
    
  





  
  1
  
    
//


  		




  
  2
  
    
// Toto je popisný soubor pro popis obsahu adresáře


  		




  
  3
  
    
//


  		




  
  4
  
    

  		




  
  5
  
    
[InfoShortDescription.en]


  		




  
  6
  
    
  Xilinx ChipScope Demo


  		




  
  7
  
    

  		




  
  8
  
    
[InfoShortDescription.cs]


  		




  
  9
  
    
  Xilinx ChipScope Demo


  		




  
  10
  
    
  


  		




  
  11
  
    
[InfoLongDescription.en]


  		




  
  12
  
    
  ChipScope IP Core from Xilinx company enable us to add pretty


  		




  
  13
  
    
  powerful logic analyser into our own FPGA design. It is necessary


  		




  
  14
  
    
  to have a valid license for generation of bitfile but not for


  		




  
  15
  
    
  usage and debugging. The text here shows a realisation of


  		




  
  16
  
    
  an universal logic analyser in Spartan device  on MLAB


  		




  
  17
  
    
  board S3AN01. It shows the use of Xilinx Virtual Cable technology


  		




  
  18
  
    
  as well.


  		




  
  19
  
    
  The maximum achieved sampling rate is 170 MS/s with 9 or 18 input channels.


  		




  
  20
  
    

  		




  
  21
  
    
[InfoLongDescription.cs]


  		




  
  22
  
    
  IP jádro ChipScope firmy Xilinx umožňuje vložit do vlastního návrhu


  		




  
  23
  
    
  FPGA obvodu docela výkonný logický analyzátor. K překladu takového


  		




  
  24
  
    
  obvodu potřebujeme příslušnou licenci, ale pro použití (ladění)


  		




  
  25
  
    
  už ne. Uvedený článek ukazuje realizaci univerzálního logického


  		




  
  26
  
    
  analyzátoru v obvodu Spartan na desce S3AN01 ze stavebnice MLAB


  		




  
  27
  
    
  a to současně s použitím technologie Xilinx Virtual Cable


  		




  
  28
  
    
  s přenosem JTAG příkazů po síti.


  		




  
  29
  
    
  Maximální dosažená rychlost vzorkování je 170 MS/s na 9 nebo 18 kanálech.


  		




  
  30
  
    

  		




  
  31
  
    
[SortPreferences]


  		




  
  32
  
    

  		




  
  33
  
    
[End]


  		












  

    
      Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/FindXilinxTools.cmd
    
  





  
  1
  
    
@echo off


  		




  
  2
  
    
rem Finds installation of Xilinx tools and makes necessary env settings


  		




  
  3
  
    

  		




  
  4
  
    
rem ----- Set 32/64 bit


  		




  
  5
  
    
if Defined PROCESSOR_ARCHITEW6432 (


  		




  
  6
  
    
	Set ProcArch=%PROCESSOR_ARCHITEW6432%


  		




  
  7
  
    
) else (


  		




  
  8
  
    
	Set ProcArch=%PROCESSOR_ARCHITECTURE%


  		




  
  9
  
    
)


  		




  
  10
  
    
if "%ProcArch%" == "AMD64" Set ProcArch=x64


  		




  
  11
  
    
rem echo %ProcArch%


  		




  
  12
  
    
if "%ProcArch%" == "x64" (


  		




  
  13
  
    
  set fileXilinxSet=settings64.bat


  		




  
  14
  
    
) else (


  		




  
  15
  
    
  set fileXilinxSet=settings32.bat


  		




  
  16
  
    
)


  		




  
  17
  
    

  		




  
  18
  
    
rem ----- Find Xilinx directory


  		




  
  19
  
    
echo Find Xilinx Tools


  		




  
  20
  
    
for %%i in (C:\SW32\Xilinx C:\Xilinx) do (


  		




  
  21
  
    
  rem Take the last directory


  		




  
  22
  
    
  for /F %%j in ('dir %%i\*.* /AD /B /O-N') do (


  		




  
  23
  
    
    for %%k in (%%i\%%j\ISE_DS) do (


  		




  
  24
  
    
      rem echo %%j\%fileXilinxSet%


  		




  
  25
  
    
      if exist %%k\%fileXilinxSet% (


  		




  
  26
  
    
        echo Found at %%k\%fileXilinxSet%


  		




  
  27
  
    
        call %%k\%fileXilinxSet%


  		




  
  28
  
    
	set XILINX_VERSION=%%j


  		




  
  29
  
    
	if not "%1"=="" (


  		




  
  30
  
    
		rem Call script


  		




  
  31
  
    
		call %1


  		




  
  32
  
    
	) else (


  		




  
  33
  
    
		rem Just set env


  		




  
  34
  
    
	        goto Label1


  		




  
  35
  
    
	)


  		




  
  36
  
    
      )


  		




  
  37
  
    
    )


  		




  
  38
  
    
  )


  		




  
  39
  
    
)


  		




  
  40
  
    
:Label1


  		












  

    
      Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/run_ChipScopeAnalyser_18_1024.cmd
    
  





  
  1
  
    
@echo off


  		




  
  2
  
    
rem


  		




  
  3
  
    
rem Script for starting Analyser.exe with predefined settings.


  		




  
  4
  
    
rem The script starts mlab_xvcd.exe deamon for users who use


  		




  
  5
  
    
rem Xilinx Virtual Cable and FTDI JTAG cable. Those users


  		




  
  6
  
    
rem should select in ChipScope Analyser setting


  		




  
  7
  
    
rem JTAG Chain / Open Plug-in.


  		




  
  8
  
    
rem 


  		




  
  9
  
    

  		




  
  10
  
    

  		




  
  11
  
    
rem ----- Run Xilinx Virtual Cable Daemon (as separate process)


  		




  
  12
  
    
rem Run it if you use XVC cable connected to the local computer


  		




  
  13
  
    
rem To start the daemon if already runnig does no harm


  		




  
  14
  
    
if exist ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe (


  		




  
  15
  
    
	start ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe


  		




  
  16
  
    
)


  		




  
  17
  
    

  		




  
  18
  
    

  		




  
  19
  
    
rem ----- Find and Set Xilinx Tools


  		




  
  20
  
    
call FindXilinxTools.cmd


  		




  
  21
  
    

  		




  
  22
  
    

  		




  
  23
  
    
rem ----- Run ChipScope Analyser


  		




  
  24
  
    
analyzer.exe -project ..\ANALYSER\Analyser_18_1024.cpj -init ..\ANALYSER\Analyser.ini


  		












  

    
      Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_CoreGen.cmd
    
  





  
  1
  
    
@echo off


  		




  
  2
  
    
rem	Batch to (re)generate IP cores (ChipScope components)


  		




  
  3
  
    
rem	Run once, takes several minutes to finish.


  		




  
  4
  
    
rem


  		




  
  5
  
    
rem	Do not modify source files directory structure


  		




  
  6
  
    
rem


  		




  
  7
  
    
rem	Tested with Xilinx ISE WebPack 13.3 and 14.5


  		




  
  8
  
    
rem	This step does not require ChipScope License


  		




  
  9
  
    
rem


  		




  
  10
  
    

  		




  
  11
  
    

  		




  
  12
  
    
rem ----- Find and Set Xilinx Tools


  		




  
  13
  
    
call FindXilinxTools.cmd


  		




  
  14
  
    

  		




  
  15
  
    

  		




  
  16
  
    
rem ----- Run Coregen in paralel (we all have multicore cpu don't we?)


  		




  
  17
  
    
rem Unfortunately CoreGen can't be run in parallel.


  		




  
  18
  
    
rem There is some conflict (You cenrtainly know what all that cores are good for...)


  		




  
  19
  
    
rem start "CoreGen ICON"        coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ICON.xco        -r


  		




  
  20
  
    
rem start "CoreGen ILA 18x1024" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_18_1024.xco -r


  		




  
  21
  
    
rem start "CoreGen ILA 9x2048"  coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_9_2048.xco  -r


  		




  
  22
  
    
rem start "CoreGen VIO FreqSel" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_FreqSel.xco -r


  		




  
  23
  
    
rem start "CoreGen VIO UserOut" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_UserOut.xco -r


  		




  
  24
  
    

  		




  
  25
  
    

  		




  
  26
  
    
rem ----- Run CoreGen one after one for all components


  		




  
  27
  
    
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ICON.xco        -r


  		




  
  28
  
    
if %errorlevel% NEQ 0 (


  		




  
  29
  
    
	echo.


  		




  
  30
  
    
	echo.


  		




  
  31
  
    
	echo ERROR in coregen ChipScope_ICON


  		




  
  32
  
    
	echo ===============================


  		




  
  33
  
    
	pause


  		




  
  34
  
    
	exit 1


  		




  
  35
  
    
) 


  		




  
  36
  
    

  		




  
  37
  
    
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_18_1024.xco -r


  		




  
  38
  
    
if %errorlevel% NEQ 0 (


  		




  
  39
  
    
	echo.


  		




  
  40
  
    
	echo.


  		




  
  41
  
    
	echo ERROR in coregen ChipScope_ILA_18_1024


  		




  
  42
  
    
	echo ======================================


  		




  
  43
  
    
	pause


  		




  
  44
  
    
	exit 1


  		




  
  45
  
    
) 


  		




  
  46
  
    

  		




  
  47
  
    
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_9_2048.xco  -r


  		




  
  48
  
    
if %errorlevel% NEQ 0 (


  		




  
  49
  
    
	echo.


  		




  
  50
  
    
	echo.


  		




  
  51
  
    
	echo ERROR in coregen ChipScope_ILA_9_2048


  		




  
  52
  
    
	echo =====================================


  		




  
  53
  
    
	pause


  		




  
  54
  
    
	exit 1


  		




  
  55
  
    
) 


  		




  
  56
  
    

  		




  
  57
  
    
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_FreqSel.xco -r


  		




  
  58
  
    
if %errorlevel% NEQ 0 (


  		




  
  59
  
    
	echo.


  		




  
  60
  
    
	echo.


  		




  
  61
  
    
	echo ERROR in coregen ChipScope_VIO_FreqSel


  		




  
  62
  
    
	echo ======================================


  		




  
  63
  
    
	pause


  		




  
  64
  
    
	exit 1


  		




  
  65
  
    
) 


  		




  
  66
  
    

  		




  
  67
  
    
coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_UserOut.xco -r


  		




  
  68
  
    
if %errorlevel% NEQ 0 (


  		




  
  69
  
    
	echo.


  		




  
  70
  
    
	echo.


  		




  
  71
  
    
	echo ERROR in coregen ChipScope_VIO_UserOut


  		




  
  72
  
    
	echo ======================================


  		




  
  73
  
    
	pause


  		




  
  74
  
    
	exit 1


  		




  
  75
  
    
) 


  		




  
  76
  
    

  		




  
  77
  
    

  		




  
  78
  
    
rem ----- Finished


  		




  
  79
  
    
rm coregen.log


  		




  
  80
  
    
echo.


  		




  
  81
  
    
echo CoreGen Finished with no Errors


  		












  

    
      Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_S3AN01_ChipScope.cmd
    
  





  
  1
  
    
@echo off


  		




  
  2
  
    
rem	Batch generates bitfile for Logic Analyser Demo


  		




  
  3
  
    
rem


  		




  
  4
  
    
rem	Parameters:


  		




  
  5
  
    
rem


  		




  
  6
  
    
rem		18x1024|9x2048 ... select analyser size (width and depth)


  		




  
  7
  
    
rem	


  		




  
  8
  
    
rem	Do not modify srouce files directory structure


  		




  
  9
  
    
rem


  		




  
  10
  
    
rem	Tested with Xilinx ISE WebPack 14.5 with ChipScope License


  		




  
  11
  
    
rem


  		




  
  12
  
    

  		




  
  13
  
    
rem ----- first parameter


  		




  
  14
  
    
set product=%1%


  		




  
  15
  
    
if "%product%"=="18x1024" (


  		




  
  16
  
    
	echo 18x1024


  		




  
  17
  
    
) else if "%product%" == "9x2048" (


  		




  
  18
  
    
	echo 9x2048


  		




  
  19
  
    
) else (


  		




  
  20
  
    
	echo Missing parameter %product%


  		




  
  21
  
    
  	echo usage: %0% 18x1024^|9x2048


  		




  
  22
  
    
	pause 


  		




  
  23
  
    
	exit 1


  		




  
  24
  
    
)


  		




  
  25
  
    
echo.


  		




  
  26
  
    
echo Product: %product%


  		




  
  27
  
    
echo.


  		




  
  28
  
    

  		




  
  29
  
    
rem ----- Set core (top VHDL entity) name


  		




  
  30
  
    
set core=S3AN01_ChipScope


  		




  
  31
  
    

  		




  
  32
  
    
rem ----- Set FPGA part


  		




  
  33
  
    
set fpgaPart=xc3s50an-tqg144-4


  		




  
  34
  
    

  		




  
  35
  
    
rem ----- Find and Set Xilinx Tools


  		




  
  36
  
    
call FindXilinxTools.cmd


  		




  
  37
  
    

  		




  
  38
  
    
rem ----- Set WORK dir


  		




  
  39
  
    
if exist WORK_%core%_%product% rmdir /S /Q WORK_%core%_%product%


  		




  
  40
  
    
mkdir    WORK_%core%_%product%


  		




  
  41
  
    
cd       WORK_%core%_%product%


  		




  
  42
  
    

  		




  
  43
  
    
rem ----- Set TEMP dir (relative to WORK dir)


  		




  
  44
  
    
mkdir    TMP


  		




  
  45
  
    
set      TMP=TMP


  		




  
  46
  
    

  		




  
  47
  
    
rem ----- INPUT UCF and VHDL files (linux format c:/.../... )


  		




  
  48
  
    
set srcPath=../..


  		




  
  49
  
    
set ucfFile=VHDL/S3AN01_ChipScope.ucf


  		




  
  50
  
    

  		




  
  51
  
    
echo vhdl work "%srcPath%/COREGEN/ChipScope_ICON.vhd"		> srcFiles.prj


  		




  
  52
  
    
echo vhdl work "%srcPath%/COREGEN/ChipScope_VIO_FreqSel.vhd"	>>srcFiles.prj	


  		




  
  53
  
    
echo vhdl work "%srcPath%/COREGEN/ChipScope_ILA_9_2048.vhd"	>>srcFiles.prj	


  		




  
  54
  
    

  		




  
  55
  
    
echo vhdl work "%srcPath%/VHDL/S3AN01_ChipScope.vhd"		>>srcFiles.prj


  		




  
  56
  
    

  		




  
  57
  
    
rem ----- SET XST setting


  		




  
  58
  
    
echo set -xsthdpdir "xst"					> setXst.xst


  		




  
  59
  
    
echo run							>>setXst.xst


  		




  
  60
  
    
echo -ifn "srcFiles.prj"					>>setXst.xst


  		




  
  61
  
    
echo -ofn %core%						>>setXst.xst


  		




  
  62
  
    
echo -ofmt NGC							>>setXst.xst


  		




  
  63
  
    
echo -top %core%						>>setXst.xst


  		




  
  64
  
    
echo -iob True							>>setXst.xst


  		




  
  65
  
    
echo -p %fpgaPart%						>>setXst.xst


  		




  
  66
  
    

  		




  
  67
  
    
if "%product%"=="18x1024" (


  		




  
  68
  
    
	echo -generics { ILA_WIDE=TRUE  }			>>setXst.xst 


  		




  
  69
  
    
) else (


  		




  
  70
  
    
	echo -generics { ILA_WIDE=FALSE  }			>>setXst.xst 


  		




  
  71
  
    
)


  		




  
  72
  
    

  		




  
  73
  
    
rem ----- SET BITGEN setting


  		




  
  74
  
    
echo -w				> setBitGen.ut


  		




  
  75
  
    
echo -g ConfigRate:25		>>setBitGen.ut


  		




  
  76
  
    
echo -g UnusedPin:PullUp	>>setBitGen.ut


  		




  
  77
  
    
echo -g DriveDone:Yes		>>setBitGen.ut


  		




  
  78
  
    

  		




  
  79
  
    

  		




  
  80
  
    
call xst -ifn "setXst.xst" -ofn "%core%.log" 


  		




  
  81
  
    
if %errorlevel% NEQ 0 (


  		




  
  82
  
    
	echo.


  		




  
  83
  
    
	echo.


  		




  
  84
  
    
	echo ERROR in xst


  		




  
  85
  
    
	echo ============


  		




  
  86
  
    
	pause


  		




  
  87
  
    
	exit 1


  		




  
  88
  
    
) 


  		




  
  89
  
    

  		




  
  90
  
    
call ngdbuild -intstyle ise -dd _ngo -sd ../../COREGEN -nt timestamp -uc "%srcPath%/%ucfFile%" -p %fpgaPart% %core%.ngc %core%.ngd


  		




  
  91
  
    
if %errorlevel% NEQ 0 (


  		




  
  92
  
    
	echo.


  		




  
  93
  
    
	echo.


  		




  
  94
  
    
	echo ERROR in ngdbuild


  		




  
  95
  
    
	echo =================


  		




  
  96
  
    
	pause


  		




  
  97
  
    
	exit 1


  		




  
  98
  
    
) 


  		




  
  99
  
    

  		




  
  100
  
    
call map -intstyle ise -p %fpgaPart% -cm area -ir off -pr off -c 100 -o %core%.ncd %core%.ngd %core%.pcf 


  		




  
  101
  
    
if %errorlevel% NEQ 0 (


  		




  
  102
  
    
	echo.


  		




  
  103
  
    
	echo.


  		




  
  104
  
    
	echo ERROR in map


  		




  
  105
  
    
	echo ============


  		




  
  106
  
    
	pause


  		




  
  107
  
    
	exit 1


  		




  
  108
  
    
) 


  		




  
  109
  
    

  		




  
  110
  
    
call par -w -intstyle ise -ol high -t 1 %core%.ncd %core%.ncd %core%.pcf


  		




  
  111
  
    
if %errorlevel% NEQ 0 (


  		




  
  112
  
    
	echo.


  		




  
  113
  
    
	echo.


  		




  
  114
  
    
	echo ERROR in par


  		




  
  115
  
    
	echo ============


  		




  
  116
  
    
	pause


  		




  
  117
  
    
	exit 1


  		




  
  118
  
    
) 


  		




  
  119
  
    

  		




  
  120
  
    
call trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml %core%.twx %core%.ncd -o %core%.twr %core%.pcf


  		




  
  121
  
    
if %errorlevel% NEQ 0 (


  		




  
  122
  
    
	echo.


  		




  
  123
  
    
	echo.


  		




  
  124
  
    
	echo ERROR in trace


  		




  
  125
  
    
	echo ==============


  		




  
  126
  
    
	pause


  		




  
  127
  
    
	exit 1


  		




  
  128
  
    
) 


  		




  
  129
  
    

  		




  
  130
  
    
call bitgen -f "setBitGen.ut" %core%.ncd


  		




  
  131
  
    
if %errorlevel% NEQ 0 (


  		




  
  132
  
    
	echo.


  		




  
  133
  
    
	echo.


  		




  
  134
  
    
	echo ERROR in bidgen


  		




  
  135
  
    
	echo ===============


  		




  
  136
  
    
	pause


  		




  
  137
  
    
	exit 1


  		




  
  138
  
    
) 


  		




  
  139
  
    

  		




  
  140
  
    
rem ----- Verify Timing


  		




  
  141
  
    
findstr /B /C:"All constraints were met." %core%.par


  		




  
  142
  
    
if %errorlevel% NEQ 0 (


  		




  
  143
  
    
	echo.


  		




  
  144
  
    
	echo.


  		




  
  145
  
    
	echo ERROR in Timing


  		




  
  146
  
    
	echo ===============


  		




  
  147
  
    
	pause


  		




  
  148
  
    
	exit 1


  		




  
  149
  
    
)


  		




  
  150
  
    

  		




  
  151
  
    
if exist ..\BIN\%XILINX_VERSION% (


  		




  
  152
  
    
	rem ----- Copy result to BIN\{ISE_VER} directory


  		




  
  153
  
    
	copy /Y %core%.bit ..\BIN\%XILINX_VERSION%\%core%_%product%.bit


  		




  
  154
  
    
	rem copy /Y %core%.par ..\BIN\%XILINX_VERSION%\%core%_%product%.par


  		




  
  155
  
    
	rem ----- Remove WORK dir


  		




  
  156
  
    
	rem (bitgen starts wbtc.exe as a secondary process)


  		




  
  157
  
    
	cd ..


  		




  
  158
  
    

  		




  
  159
  
    
	rem Wait for xwebtalk has finished its work (sending stat data to Xilinx)


  		




  
  160
  
    
	echo | set /p=Waiting for WebTalk... 


  		




  
  161
  
    
	:StartLoop


  		




  
  162
  
    
		tasklist | findstr /i /c:"wbtc.exe" > nul


  		




  
  163
  
    
		if %errorlevel% NEQ 0 (


  		




  
  164
  
    
			goto ExitLoop


  		




  
  165
  
    
		)


  		




  
  166
  
    
		sleep 1


  		




  
  167
  
    
		echo | set /p=* 


  		




  
  168
  
    
		goto StartLoop


  		




  
  169
  
    
	)


  		




  
  170
  
    
	:ExitLoop


  		




  
  171
  
    

  		




  
  172
  
    
	rem	Tohle nefunguje, proto?e v?stup wmic je UTF-16 a to finstr neum?


  		




  
  173
  
    
	rem	wmic process | findstr /c:"%core%_%product%"


  		




  
  174
  
    
	rem 	wmic process > ..\"%core%_%product%".wmic


  		




  
  175
  
    

  		




  
  176
  
    
	rmdir /S /Q WORK_%core%_%product%


  		




  
  177
  
    
	exit 0


  		




  
  178
  
    
)


  		




  
  179
  
    
exit 1


  		












  

    
      Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_all.cmd
    
  





  
  1
  
    
@echo off


  		




  
  2
  
    
rem	Batch to generate bitstream


  		




  
  3
  
    
rem


  		




  
  4
  
    
rem		S3AN01_ChipScope_18x1024.bit


  		




  
  5
  
    
rem		S3AN01_ChipScope_9x2048.bit


  		




  
  6
  
    
rem


  		




  
  7
  
    
rem	Do not modify srouce files directory structure


  		




  
  8
  
    
rem


  		




  
  9
  
    
rem	Tested with Xilinx ISE WebPack 14.5 with ChipScope License


  		




  
  10
  
    
rem


  		




  
  11
  
    

  		




  
  12
  
    
rem ----- Check if ChipScope IP Cores are ready


  		




  
  13
  
    
if not exist ..\COREGEN\ChipScope_ICON.vhd		goto coregen


  		




  
  14
  
    
if not exist ..\COREGEN\ChipScope_ILA_18_1024.vhd	goto coregen


  		




  
  15
  
    
if not exist ..\COREGEN\ChipScope_ILA_9_2048.vhd	goto coregen


  		




  
  16
  
    
if not exist ..\COREGEN\ChipScope_VIO_FreqSel.vhd	goto coregen


  		




  
  17
  
    
if not exist ..\COREGEN\ChipScope_VIO_UserOut.vhd	goto coregen


  		




  
  18
  
    
goto next


  		




  
  19
  
    
	:coregen


  		




  
  20
  
    
	rem ----- Regenerate ChipScope IP Cores


  		




  
  21
  
    
	echo.


  		




  
  22
  
    
	echo Missing ChipScope IP Core output files


  		




  
  23
  
    
	echo Regenerating will take a long time (5 minutes on i5-3770)


  		




  
  24
  
    
	echo.


  		




  
  25
  
    
	pause


  		




  
  26
  
    
	call make_CoreGen.cmd


  		




  
  27
  
    
:next


  		




  
  28
  
    

  		




  
  29
  
    
rem ----- Clear target directory


  		




  
  30
  
    
rmdir /S /Q BIN 2> nul


  		




  
  31
  
    
mkdir BIN


  		




  
  32
  
    

  		




  
  33
  
    
rem ----- Get Current date and time


  		




  
  34
  
    
for /F "Tokens=2-4 Delims=. " %%A in ("%DATE%") do (


  		




  
  35
  
    
  set CurDate=%%C_%%B_%%A


  		




  
  36
  
    
)


  		




  
  37
  
    
for /F "Tokens=1-2 Delims=:,. " %%D in ("%TIME: =0%") do (


  		




  
  38
  
    
  set CurTime=%%D_%%E


  		




  
  39
  
    
)


  		




  
  40
  
    

  		




  
  41
  
    
rem ----- Find and Set Xilinx Tools


  		




  
  42
  
    
call FindXilinxTools.cmd


  		




  
  43
  
    
mkdir BIN\%XILINX_VERSION%


  		




  
  44
  
    

  		




  
  45
  
    
rem ----- Create Version metafile


  		




  
  46
  
    
echo TimeStamp:     %CurDate%__%CurTime%>  BIN\%XILINX_VERSION%\Version


  		




  
  47
  
    
echo ComputerName:  %COMPUTERNAME%>> BIN\%XILINX_VERSION%\Version


  		




  
  48
  
    
echo ISE Version:   %XILINX_VERSION%>> BIN\%XILINX_VERSION%\Version


  		




  
  49
  
    
echo ReleaseInfo:   None>> BIN\%XILINX_VERSION%\Version


  		




  
  50
  
    

  		




  
  51
  
    
rem ----- Compile variants (paralel run)


  		




  
  52
  
    
start "compile S3AN01_ChipScope_18x1024"  make_S3AN01_ChipScope.cmd 18x1024


  		




  
  53
  
    
start "compile S3AN01_ChipScope_9x2048"   make_S3AN01_ChipScope.cmd 9x2048


  		












  

    
      Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/run_ChipScopeAnalyser_9_2048.cmd
    
  





  
  1
  
    
@echo off


  		




  
  2
  
    
rem


  		




  
  3
  
    
rem Script for starting Analyser.exe with predefined settings.


  		




  
  4
  
    
rem The script starts mlab_xvcd.exe deamon for users who use


  		




  
  5
  
    
rem Xilinx Virtual Cable and FTDI JTAG cable. Those users


  		




  
  6
  
    
rem should select in ChipScope Analyser setting


  		




  
  7
  
    
rem JTAG Chain / Open Plug-in.


  		




  
  8
  
    
rem 


  		




  
  9
  
    

  		




  
  10
  
    

  		




  
  11
  
    
rem ----- Run Xilinx Virtual Cable Daemon (as separate process)


  		




  
  12
  
    
rem Run it if you use XVC cable connected to the local computer


  		




  
  13
  
    
rem To start the daemon if already runnig does no harm


  		




  
  14
  
    
if exist ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe (


  		




  
  15
  
    
	start ..\..\XILINX_XVC\XVC_SOFTWARE\XVC_1x\BIN\mlab_xvcd.exe


  		




  
  16
  
    
)


  		




  
  17
  
    

  		




  
  18
  
    

  		




  
  19
  
    
rem ----- Find and Set Xilinx Tools


  		




  
  20
  
    
call FindXilinxTools.cmd


  		




  
  21
  
    

  		




  
  22
  
    

  		




  
  23
  
    
rem ----- Run ChipScope Analyser


  		




  
  24
  
    
analyzer.exe -project ..\ANALYSER\Analyser_9_2048.cpj -init ..\ANALYSER\Analyser.ini


  		












  

    
      Modules/CPLD_FPGA/XILINX_CHIPSCOPE/VHDL/S3AN01_ChipScope.vhd
    
  





  
  1
  
    
-- ========================================================================


  		




  
  2
  
    
-- 


  		




  
  3
  
    
-- S3AN01_ChipScope


  		




  
  4
  
    
--


  		




  
  5
  
    
-- Logic Analyser based on Xilinx ChipScope IP Core for S3AN01 Board


  		




  
  6
  
    
--


  		




  
  7
  
    
-- (c) miho 2013 / http://www.mlab.cz/PermaLink/XILINX_ChipScope


  		




  
  8
  
    
--


  		




  
  9
  
    
-- Demo application contains some Clock Logic (DCM block and 


  		




  
  10
  
    
-- clock switch to be able to set different sample clocks).


  		




  
  11
  
    
-- The main function is ChipScope Logic Analyser with 16 data inputs


  		




  
  12
  
    
-- (with 24 bit trigger) and storage for 1024 Data Samples.


  		




  
  13
  
    
--


  		




  
  14
  
    
-- Sampling clock is selectable to 170/100/50/20/10/5/2/1MHz


  		




  
  15
  
    
--


  		




  
  16
  
    
-- To implement the design the ChipScope license is required.


  		




  
  17
  
    
--


  		




  
  18
  
    
-- To use (the logic analyser) no speceial license is needed,


  		




  
  19
  
    
-- WebPack ISE or Lab Tools is enough). Requires some compatible


  		




  
  20
  
    
-- JTAG cable. Compatible with MLAB Xilinx Virtual Cable as well


  		




  
  21
  
    
-- http://www.mlab.cz/PermaLink/XILINX_XVC


  		




  
  22
  
    
--


  		




  
  23
  
    
-- Device:		Spartan3AN XC3S50AN-4TQG144C


  		




  
  24
  
    
--


  		




  
  25
  
    
-- Software:	ISE WebPack 14.5


  		




  
  26
  
    
--


  		




  
  27
  
    
-- ========================================================================


  		




  
  28
  
    

  		




  
  29
  
    

  		




  
  30
  
    
-- Standard Library


  		




  
  31
  
    
library IEEE;


  		




  
  32
  
    
use IEEE.STD_LOGIC_1164.ALL;


  		




  
  33
  
    
use IEEE.numeric_std.ALL;


  		




  
  34
  
    

  		




  
  35
  
    

  		




  
  36
  
    
-- Xilinx Library (necessary for DMC and other Xilinx blocks)


  		




  
  37
  
    
library UNISIM;


  		




  
  38
  
    
use UNISIM.VComponents.all;


  		




  
  39
  
    

  		




  
  40
  
    

  		




  
  41
  
    
-- Interface


  		




  
  42
  
    
entity S3AN01_ChipScope is


  		




  
  43
  
    
	generic(


  		




  
  44
  
    
		ILA_WIDE:	boolean := TRUE;										--	TRUE/FALSE	-> 18bit x 1024 / 9bit x 2048 logic analyser


  		




  
  45
  
    
		MUXCOUNT:	integer := 100_000									--	LED Display Multiplex Clock Divider


  		




  
  46
  
    
	);


  		




  
  47
  
    
	port(


  		




  
  48
  
    
		-- Main Clock


  		




  
  49
  
    
		CLK100MHz:	in		std_logic;										--	100MHz external xtal clock source


  		




  
  50
  
    

  		




  
  51
  
    
		-- Mode Signals (usualy not used)


  		




  
  52
  
    
		VS:			out	std_logic_vector(2 downto 0);				--	SPI Flash Vendor Mode Select


  		




  
  53
  
    

  		




  
  54
  
    
		-- Dipswitch Inputs


  		




  
  55
  
    
		DIPSW:		in		std_logic_vector(7 downto 0);


  		




  
  56
  
    

  		




  
  57
  
    
		-- LED Bar Outputs


  		




  
  58
  
    
		LED:			out	std_logic_vector(7 downto 0);


  		




  
  59
  
    

  		




  
  60
  
    
		--	LED Display (8 digits with 7 segments and decimal point)


  		




  
  61
  
    
		LD_CA_n:		out	std_logic_vector(7 downto 0);


  		




  
  62
  
    
		LD_SEG_n:	out	std_logic_vector(7 downto 0);


  		




  
  63
  
    

  		




  
  64
  
    
		-- Bank 1 Pins Inputs


  		




  
  65
  
    
		P:				in		std_logic_vector(24 downto 0);


  		




  
  66
  
    

  		




  
  67
  
    
		--	Diferencial Signals on 4 pin header (J7)


  		




  
  68
  
    
		DIF1P:		inout	std_logic;


  		




  
  69
  
    
		DIF1N:		inout	std_logic;


  		




  
  70
  
    
		DIF2P:		inout	std_logic;


  		




  
  71
  
    
		DIF2N:		inout	std_logic


  		




  
  72
  
    
	);


  		




  
  73
  
    
end S3AN01_ChipScope;


  		




  
  74
  
    

  		




  
  75
  
    

  		




  
  76
  
    
-- Implementation


  		




  
  77
  
    
architecture S3AN01_ChipScope_a of S3AN01_ChipScope is


  		




  
  78
  
    

  		




  
  79
  
    
	--	Clock Signals


  		




  
  80
  
    
	--	=============


  		




  
  81
  
    

  		




  
  82
  
    
	--	DCM Signals


  		




  
  83
  
    
	signal DCM_CLK0:				std_logic;														--	DCM output for feedback


  		




  
  84
  
    
	signal DCM_CLKFX:				std_logic;														--	DCM output of the fastest clock 


  		




  
  85
  
    
	signal CLK_FAST:				std_logic;														--	Main clock for ILA


  		




  
  86
  
    
	signal CLK_FAST_Q:			std_logic;														--	Auxiliary signal (for CLK_FAST sent to pin)


  		




  
  87
  
    

  		




  
  88
  
    
	--	100MHz Clock Switch


  		




  
  89
  
    
	-- CLK100MHz Clock Domain


  		




  
  90
  
    
	signal CLK100MHz_CE:			std_logic;														--	Gate Signal for slow dwn of the 100MHz clock


  		




  
  91
  
    
	signal CLK100MHz_Gated:		std_logic;														--	Gated Clocks


  		




  
  92
  
    
	signal CLK100MHz_CE_Cnt:	unsigned(6 downto 0) := (others => '0');				--	Gate Signal Counter (min frequency is 1/100 of CLK100MHz


  		




  
  93
  
    

  		




  
  94
  
    
	--	1 Hot Clock Select Signals


  		




  
  95
  
    
	-- CLK100MHz Clock Domain


  		




  
  96
  
    
	signal SET_CLK_MAX:			std_logic := '0';												--	Clock Select Signal - Maximim (150-170Mhz)


  		




  
  97
  
    
	signal SET_CLK_100MHz:		std_logic := '1';												--	Clock Select Signal - 100MHz


  		




  
  98
  
    
	signal SET_CLK_50MHz:		std_logic := '0';												--	Clock Select Signal - 50MHz


  		




  
  99
  
    
	signal SET_CLK_20Mhz:		std_logic := '0';												--	Clock Select Signal - 20MHz


  		




  
  100
  
    
	signal SET_CLK_10Mhz:		std_logic := '0';												--	Clock Select Signal - 10MHz


  		




  
  101
  
    
	signal SET_CLK_5Mhz:			std_logic := '0';												--	Clock Select Signal - 5MHz


  		




  
  102
  
    
	signal SET_CLK_2Mhz:			std_logic := '0';												--	Clock Select Signal - 2MHz


  		




  
  103
  
    
	signal SET_CLK_1Mhz:			std_logic := '0';												--	Clock Select Signal - 1MHz


  		




  
  104
  
    

  		




  
  105
  
    
	--	Signals from and to ChipScope Virtual IO (set and display frequency)


  		




  
  106
  
    
	-- CLK_FAST and CLK100MHz time domain


  		




  
  107
  
    
	signal SYNC_IN:				std_logic_vector(7 downto 0);								--	Input to ChipScope VIO


  		




  
  108
  
    
	signal SYNC_OUT:				std_logic_vector(7 downto 0);								--	Output from ChipScope VIO


  		




  
  109
  
    
	signal SW_SYNC:				std_logic_vector(7 downto 0) := (others => '0');	--	Asyn inputs synced


  		




  
  110
  
    

  		




  
  111
  
    

  		




  
  112
  
    
	--	LED Ouput with time multiplex


  		




  
  113
  
    
	--	=============================


  		




  
  114
  
    

  		




  
  115
  
    
	signal WideBCD:				std_logic_vector(2*5-1 downto 0);						--	Constant width of ILA in BCD (2 char wide)


  		




  
  116
  
    
	signal FrequencyBCD:			std_logic_vector(3*5-1 downto 0);						--	Selected frequency in BCD (3 char wide)


  		




  
  117
  
    
	signal Code:					std_logic_vector(4 downto 0);								--	BCD to 7 Segment Decoder Output


  		




  
  118
  
    
	signal Segments:				std_logic_vector(0 to 7);									--	LED Segment Output


  		




  
  119
  
    

  		




  
  120
  
    
	--	Time Multiplex


  		




  
  121
  
    
	signal MuxCounter:			unsigned(31 downto 0)			:=	(others => '0');	--	LED Multiplex - Multiplex Clock Divider


  		




  
  122
  
    
	signal LedEnable:				std_logic;														--	LED Display Brightness


  		




  
  123
  
    
	signal Digits:					std_logic_vector(7 downto 0)	:=	X"01";				--	LED Multiplex - Digit Counter - LED Digit Output


  		




  
  124
  
    

  		




  
  125
  
    

  		




  
  126
  
    
	--	Test Generator signals


  		




  
  127
  
    
	--	======================


  		




  
  128
  
    
	


  		




  
  129
  
    
	signal Counter:				std_logic_vector(7 downto 0);								--	Counter


  		




  
  130
  
    

  		




  
  131
  
    

  		




  
  132
  
    
	--	ChipScope Signals


  		




  
  133
  
    
	--	=================


  		




  
  134
  
    

  		




  
  135
  
    
	-- Input data


  		




  
  136
  
    
	--	CLK_FAST Clock Domain


  		




  
  137
  
    
	signal DataReg:				std_logic_vector(P'range);									--	Data and Trigger input


  		




  
  138
  
    
	


  		




  
  139
  
    
	--	Trigger Output


  		




  
  140
  
    
	signal TriggerOut:			std_logic;														--	Trigegr output from ChipScope ILA to pin


  		




  
  141
  
    

  		




  
  142
  
    
	--	User Outputs from ChipScope Virtual IO


  		




  
  143
  
    
	signal SYNC_OUT_USER:		std_logic_vector(2 downto 0);								--	Output from ChipScope VIO


  		




  
  144
  
    

  		




  
  145
  
    
	--	ChipScope Control Signals


  		




  
  146
  
    
	signal Control0:				std_logic_vector(35 downto 0);


  		




  
  147
  
    
	signal Control1:				std_logic_vector(35 downto 0);


  		




  
  148
  
    
	signal Control2:				std_logic_vector(35 downto 0);


  		




  
  149
  
    

  		




  
  150
  
    
	--	ChipScope Control Block


  		




  
  151
  
    
	component ChipScope_ICON


  		




  
  152
  
    
	port (


  		




  
  153
  
    
		CONTROL0:	inout	std_logic_vector(35 downto 0);


  		




  
  154
  
    
		CONTROL1:	inout	std_logic_vector(35 downto 0);


  		




  
  155
  
    
		CONTROL2:	inout	std_logic_vector(35 downto 0)


  		




  
  156
  
    
	);


  		




  
  157
  
    
	end component;


  		




  
  158
  
    

  		




  
  159
  
    
	-- ChipScope Virtual I/O Block


  		




  
  160
  
    
	component ChipScope_VIO_FreqSel


  		




  
  161
  
    
	port (


  		




  
  162
  
    
		CONTROL:		inout	std_logic_vector(35 downto 0);


  		




  
  163
  
    
		CLK:			in		std_logic;


  		




  
  164
  
    
		SYNC_IN:		in		std_logic_vector(7 downto 0);


  		




  
  165
  
    
		SYNC_OUT:	out	std_logic_vector(7 downto 0)


  		




  
  166
  
    
	);


  		




  
  167
  
    
	end component;


  		




  
  168
  
    

  		




  
  169
  
    
	-- ChipScope Virtual I/O Block


  		




  
  170
  
    
	component ChipScope_VIO_UserOut


  		




  
  171
  
    
	port (


  		




  
  172
  
    
		CONTROL:		inout	std_logic_vector(35 downto 0);


  		




  
  173
  
    
		CLK:			in		std_logic;


  		




  
  174
  
    
		SYNC_OUT:	out	std_logic_vector(2 downto 0)


  		




  
  175
  
    
	);


  		




  
  176
  
    
	end component;


  		




  
  177
  
    

  		




  
  178
  
    
	--	ChipScope Integrated Logic Analyser


  		




  
  179
  
    
	component ChipScope_ILA_18_1024


  		




  
  180
  
    
	port (


  		




  
  181
  
    
		CONTROL:		inout	std_logic_vector(35 downto 0);


  		




  
  182
  
    
		CLK:			in		std_logic;


  		




  
  183
  
    
		DATA:			in		std_logic_vector(17 downto 0);	-- 18 bits wide data


  		




  
  184
  
    
		TRIG0:		in		std_logic_vector(23 downto 0);


  		




  
  185
  
    
		TRIG_OUT:	out	std_logic


  		




  
  186
  
    
	);


  		




  
  187
  
    
	end component;


  		




  
  188
  
    

  		




  
  189
  
    
	--	ChipScope Integrated Logic Analyser


  		




  
  190
  
    
	component ChipScope_ILA_9_2048


  		




  
  191
  
    
	port (


  		




  
  192
  
    
		CONTROL:		inout	std_logic_vector(35 downto 0);


  		




  
  193
  
    
		CLK:			in		std_logic;


  		




  
  194
  
    
		DATA:			in		std_logic_vector(8 downto 0);		--	9 bits wide data


  		




  
  195
  
    
		TRIG0:		in		std_logic_vector(23 downto 0);


  		




  
  196
  
    
		TRIG_OUT:	out	std_logic


  		




  
  197
  
    
	);


  		




  
  198
  
    
	end component;


  		




  
  199
  
    

  		




  
  200
  
    
begin


  		




  
  201
  
    

  		




  
  202
  
    

  		




  
  203
  
    
	--	===================================================


  		




  
  204
  
    
	--	Clock Network and Clock Switching


  		




  
  205
  
    
	--	===================================================


  		




  
  206
  
    
	--


  		




  
  207
  
    
	-- The fastest clock signal is generated from 100MHz by DCM.


  		




  
  208
  
    
	-- The design maximim is 170MHz for selected device.


  		




  
  209
  
    
	--


  		




  
  210
  
    
	-- For lower frequency the 100MHz clocks are gated in BUFGCE


  		




  
  211
  
    
	--	acording to SET_CLK_xxx signals.


  		




  
  212
  
    
	--


  		




  
  213
  
    
	-- For Logic Analyser we use 170MHz from DCM or gated 100MHz


  		




  
  214
  
    
	-- switchd by BUFGMUX block.


  		




  
  215
  
    
	


  		




  
  216
  
    

  		




  
  217
  
    
	-- DCM_SP: Digital Clock Manager Circuit


  		




  
  218
  
    
	--         Spartan-3A


  		




  
  219
  
    
	-- Xilinx HDL Language Template, version 14.5


  		




  
  220
  
    
	--


  		




  
  221
  
    
	--	CLKFB without BUFG (we do not need phase relation to the original clock)


  		




  
  222
  
    
	--


  		




  
  223
  
    
	--	Design Limits (XC3S50AN-4):


  		




  
  224
  
    
	--


  		




  
  225
  
    
	--		5/3	-> 166MHz - o.k. (best 5.9ns   - 169.5MHz)


  		




  
  226
  
    
	--		17/10	-> 170MHz - o.k. (best 5.748ns - 174MHz)		<------ Used Here


  		




  
  227
  
    
	--		12/7	-> 171MHz - Timing Error


  		




  
  228
  
    
	--		 7/4	-> 175MHz - Timing Error


  		




  
  229
  
    
	--		18/10	-> 180MHz - Timing Error


  		




  
  230
  
    
	--


  		




  
  231
  
    
	DCM_SP_inst:	DCM_SP


  		




  
  232
  
    
	generic map (


  		




  
  233
  
    
		CLKDV_DIVIDE				=>	2.0,							--  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0


  		




  
  234
  
    
		CLKFX_DIVIDE				=>	10,							--  Can be any interger from 1 to 32


  		




  
  235
  
    
		CLKFX_MULTIPLY				=>	17,							--  Can be any integer from 2 to 32


  		




  
  236
  
    
		CLKIN_DIVIDE_BY_2			=>	FALSE,						--  TRUE/FALSE to enable CLKIN divide by two feature


  		




  
  237
  
    
		CLKIN_PERIOD				=>	10.0,							--  Specify period of input clock


  		




  
  238
  
    
		CLKOUT_PHASE_SHIFT		=>	"NONE",						--  Specify phase shift of "NONE", "FIXED" or "VARIABLE" 


  		




  
  239
  
    
		CLK_FEEDBACK				=>	"1X",							--  Specify clock feedback of "NONE", "1X" or "2X" 


  		




  
  240
  
    
		DESKEW_ADJUST				=>	"SYSTEM_SYNCHRONOUS",	-- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or an integer from 0 to 15


  		




  
  241
  
    
		DLL_FREQUENCY_MODE		=>	"HIGH",						-- "HIGH" or "LOW" frequency mode for DLL


  		




  
  242
  
    
		DUTY_CYCLE_CORRECTION	=>	TRUE,							--  Duty cycle correction, TRUE or FALSE


  		




  
  243
  
    
		PHASE_SHIFT					=>	0,								--  Amount of fixed phase shift from -255 to 255


  		




  
  244
  
    
		STARTUP_WAIT				=>	FALSE							--  Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE


  		




  
  245
  
    
	)


  		




  
  246
  
    
	port map (


  		




  
  247
  
    
		CLK0		=>	DCM_CLK0,		-- 0 degree DCM CLK ouptput


  		




  
  248
  
    
	--	CLK180	=>	CLK180,			-- 180 degree DCM CLK output


  		




  
  249
  
    
	--	CLK270	=>	CLK270,			-- 270 degree DCM CLK output


  		




  
  250
  
    
	--	CLK2X		=>	CLK2X,			-- 2X DCM CLK output


  		




  
  251
  
    
	--	CLK2X180	=>	CLK2X180,		-- 2X, 180 degree DCM CLK out


  		




  
  252
  
    
	--	CLK90		=>	CLK90,			-- 90 degree DCM CLK output


  		




  
  253
  
    
	--	CLKDV		=>	CLKDV,			-- Divided DCM CLK out (CLKDV_DIVIDE)


  		




  
  254
  
    
		CLKFX		=>	DCM_CLKFX,		-- DCM CLK synthesis out (M/D)


  		




  
  255
  
    
	--	CLKFX180	=>	CLKFX180,		-- 180 degree CLK synthesis out


  		




  
  256
  
    
	--	LOCKED	=>	LOCKED,			-- DCM LOCK status output


  		




  
  257
  
    
	--	PSDONE	=>	PSDONE,			-- Dynamic phase adjust done output


  		




  
  258
  
    
	--	STATUS	=>	STATUS,			-- 8-bit DCM status bits output


  		




  
  259
  
    
		CLKFB		=>	DCM_CLK0,		-- DCM clock feedback


  		




  
  260
  
    
		CLKIN		=>	CLK100MHz,		-- Clock input (from IBUFG, BUFG or DCM)


  		




  
  261
  
    
	--	PSCLK		=>	PSCLK,			-- Dynamic phase adjust clock input


  		




  
  262
  
    
	--	PSEN		=>	PSEN,				-- Dynamic phase adjust enable input


  		




  
  263
  
    
	--	PSINCDEC	=>	PSINCDEC,		-- Dynamic phase adjust increment/decrement


  		




  
  264
  
    
		RST		=>	'0'				-- DCM asynchronous reset input


  		




  
  265
  
    
	);


  		




  
  266
  
    

  		




  
  267
  
    

  		




  
  268
  
    
	--	Generate Clock Gate signal for 100MHz Clock


  		




  
  269
  
    
	process (CLK100MHz)


  		




  
  270
  
    
	begin


  		




  
  271
  
    
		if rising_edge(CLK100MHz) then


  		




  
  272
  
    
			if CLK100MHz_CE_Cnt=0 then


  		




  
  273
  
    
				CLK100MHz_CE <= '1';


  		




  
  274
  
    
				if SET_CLK_100MHz='1' then


  		




  
  275
  
    
					CLK100MHz_CE_Cnt <= to_unsigned(1-1, CLK100MHz_CE_Cnt'length);


  		




  
  276
  
    
				elsif SET_CLK_50MHz='1' then


  		




  
  277
  
    
					CLK100MHz_CE_Cnt <= to_unsigned(2-1, CLK100MHz_CE_Cnt'length);


  		




  
  278
  
    
				elsif SET_CLK_20MHz='1' then


  		




  
  279
  
    
					CLK100MHz_CE_Cnt <= to_unsigned(5-1, CLK100MHz_CE_Cnt'length);


  		




  
  280
  
    
				elsif SET_CLK_10MHz='1' then


  		




  
  281
  
    
					CLK100MHz_CE_Cnt <= to_unsigned(10-1, CLK100MHz_CE_Cnt'length);


  		




  
  282
  
    
				elsif SET_CLK_5MHz='1' then


  		




  
  283
  
    
					CLK100MHz_CE_Cnt <= to_unsigned(20-1, CLK100MHz_CE_Cnt'length);


  		




  
  284
  
    
				elsif SET_CLK_2MHz='1' then


  		




  
  285
  
    
					CLK100MHz_CE_Cnt <= to_unsigned(50-1, CLK100MHz_CE_Cnt'length);


  		




  
  286
  
    
				elsif SET_CLK_1MHz='1' then


  		




  
  287
  
    
					CLK100MHz_CE_Cnt <= to_unsigned(100-1, CLK100MHz_CE_Cnt'length);


  		




  
  288
  
    
				end if;


  		




  
  289
  
    
			else


  		




  
  290
  
    
				CLK100MHz_CE <= '0';


  		




  
  291
  
    
				CLK100MHz_CE_Cnt <= CLK100MHz_CE_Cnt-1;


  		




  
  292
  
    
			end if;


  		




  
  293
  
    
		end if;


  		




  
  294
  
    
	end process;


  		




  
  295
  
    

  		




  
  296
  
    

  		




  
  297
  
    
	-- Gate 100MHz Clocks (to produce 100/50/20/10/5/2/1 MHz)


  		




  
  298
  
    
	--	Generates 5ns pulses with 10/20/50/100/200/500/1000ns period


  		




  
  299
  
    
	BUFGCE_CLK100MHz: BUFGCE


  		




  
  300
  
    
	port map (


  		




  
  301
  
    
		I	=> CLK100MHz,			-- Clock buffer input


  		




  
  302
  
    
		CE	=> CLK100MHz_CE,		-- Clock enable input


  		




  
  303
  
    
		O	=> CLK100MHz_Gated	-- Clock buffer ouptput


  		




  
  304
  
    
	);


  		




  
  305
  
    

  		




  
  306
  
    

  		




  
  307
  
    
	--	Switch (gated) 100MHz and the fastest Clock signal from DCM


  		




  
  308
  
    
	BUFGMUX_CLK_FAST: BUFGMUX


  		




  
  309
  
    
	port map (


  		




  
  310
  
    
		I0	=>	CLK100MHz_Gated,	-- Clock0 input			--	100/50/20/10/50/20/1MHz


  		




  
  311
  
    
		I1	=>	DCM_CLKFX,			-- Clock1 input			--	170MHz


  		




  
  312
  
    
		S	=>	SET_CLK_MAX,		-- Clock select input


  		




  
  313
  
    
		O	=>	CLK_FAST				-- Clock MUX output


  		




  
  314
  
    
	);


  		




  
  315
  
    

  		




  
  316
  
    

  		




  
  317
  
    
	-- Assynchrnous inputs and inputs from CLK_FAST clock domain must be synchronised


  		




  
  318
  
    
	--		SYNC_OUT -	CLK_FAST clock domain


  		




  
  319
  
    
	--		DIPSW		-	External (off-chip) async inputs


  		




  
  320
  
    
	process (CLK100MHz)


  		




  
  321
  
    
	begin


  		




  
  322
  
    
		if rising_edge(CLK100MHz) then


  		




  
  323
  
    
			SW_SYNC <= SYNC_OUT or DIPSW;


  		




  
  324
  
    
		end if;


  		




  
  325
  
    
	end process;


  		




  
  326
  
    

  		




  
  327
  
    

  		




  
  328
  
    
	--	Ferquency Selector


  		




  
  329
  
    
	--	FSM - 1 hot


  		




  
  330
  
    
	process (CLK100MHz)


  		




  
  331
  
    
	variable TMP: std_logic_vector(SYNC_OUT'range);


  		




  
  332
  
    
	variable NEW_DATA: std_logic;


  		




  
  333
  
    
	begin


  		




  
  334
  
    
		if rising_edge(CLK100MHz) then


  		




  
  335
  
    
			TMP := (others => '0');


  		




  
  336
  
    
			NEW_DATA := '1';


  		




  
  337
  
    
			if SW_SYNC(7)='1' then


  		




  
  338
  
    
				TMP(7) := '1';


  		




  
  339
  
    
			elsif SW_SYNC(6)='1' then


  		




  
  340
  
    
				TMP(6) := '1';


  		




  
  341
  
    
			elsif SW_SYNC(5)='1' then


  		




  
  342
  
    
				TMP(5) := '1';


  		




  
  343
  
    
			elsif SW_SYNC(4)='1' then


  		




  
  344
  
    
				TMP(4) := '1';


  		




  
  345
  
    
			elsif SW_SYNC(3)='1' then


  		




  
  346
  
    
				TMP(3) := '1';


  		




  
  347
  
    
			elsif SW_SYNC(2)='1' then


  		




  
  348
  
    
				TMP(2) := '1';


  		




  
  349
  
    
			elsif SW_SYNC(1)='1' then


  		




  
  350
  
    
				TMP(1) := '1';


  		




  
  351
  
    
			elsif SW_SYNC(0)='1' then


  		




  
  352
  
    
				TMP(0) := '1';


  		




  
  353
  
    
			else


  		




  
  354
  
    
				NEW_DATA := '0';


  		




  
  355
  
    
			end if;


  		




  
  356
  
    
			if NEW_DATA='1' then


  		




  
  357
  
    
				SET_CLK_MAX		<= TMP(7);


  		




  
  358
  
    
				SET_CLK_100MHz	<= TMP(6);


  		




  
  359
  
    
				SET_CLK_50MHz	<= TMP(5);


  		




  
  360
  
    
				SET_CLK_20MHz	<= TMP(4);


  		




  
  361
  
    
				SET_CLK_10MHz	<= TMP(3);


  		




  
  362
  
    
				SET_CLK_5MHz	<= TMP(2);


  		




  
  363
  
    
				SET_CLK_2MHz	<= TMP(1);


  		




  
  364
  
    
				SET_CLK_1MHz	<= TMP(0);


  		




  
  365
  
    
			end if;


  		




  
  366
  
    
		end if;


  		




  
  367
  
    
	end process;


  		




  
  368
  
    

  		




  
  369
  
    

  		




  
  370
  
    
	--	Send selected frequency to ChipScope Virtual IO


  		




  
  371
  
    
	-- Sync it to the CLK_FAST timing domain


  		




  
  372
  
    
	SET_CLK_proc: process (CLK_FAST)


  		




  
  373
  
    
	begin


  		




  
  374
  
    
		if rising_edge(CLK_FAST) then


  		




  
  375
  
    
			SYNC_IN(7) <= SET_CLK_MAX;


  		




  
  376
  
    
			SYNC_IN(6) <= SET_CLK_100MHz;


  		




  
  377
  
    
			SYNC_IN(5) <= SET_CLK_50MHz;


  		




  
  378
  
    
			SYNC_IN(4) <= SET_CLK_20Mhz;


  		




  
  379
  
    
			SYNC_IN(3) <= SET_CLK_10Mhz;


  		




  
  380
  
    
			SYNC_IN(2) <= SET_CLK_5Mhz;


  		




  
  381
  
    
			SYNC_IN(1) <= SET_CLK_2Mhz;


  		




  
  382
  
    
			SYNC_IN(0) <= SET_CLK_1Mhz;


  		




  
  383
  
    
		end if;


  		




  
  384
  
    
	end process;


  		




  
  385
  
    

  		




  
  386
  
    

  		




  
  387
  
    
	--	===================================================


  		




  
  388
  
    
	--	ChipScope Instance - Control / Virtual IO / ILA


  		




  
  389
  
    
	--	===================================================


  		




  
  390
  
    

  		




  
  391
  
    

  		




  
  392
  
    
	--	ChipScope Instance - Control Block


  		




  
  393
  
    
	MyChipScopeICON: ChipScope_ICON


  		




  
  394
  
    
	port map (


  		




  
  395
  
    
		CONTROL0 => Control0,


  		




  
  396
  
    
		CONTROL1 => Control1,


  		




  
  397
  
    
		CONTROL2 => Control2


  		




  
  398
  
    
	);


  		




  
  399
  
    

  		




  
  400
  
    

  		




  
  401
  
    
	--	ChipScope Instance - Virtual I/O Block


  		




  
  402
  
    
	MyChipScopeVIO_FreqSel: ChipScope_VIO_FreqSel


  		




  
  403
  
    
	port map (


  		




  
  404
  
    
		CONTROL	=>	Control0,


  		




  
  405
  
    
		CLK		=>	CLK_FAST,


  		




  
  406
  
    
		SYNC_IN	=>	SYNC_IN,


  		




  
  407
  
    
		SYNC_OUT	=>	SYNC_OUT


  		




  
  408
  
    
	);


  		




  
  409
  
    

  		




  
  410
  
    

  		




  
  411
  
    
	--	ChipScope Instance - Virtual I/O Block


  		




  
  412
  
    
	MyChipScopeVIO_UserOut: ChipScope_VIO_UserOut


  		




  
  413
  
    
	port map (


  		




  
  414
  
    
		CONTROL	=>	Control1,


  		




  
  415
  
    
		CLK		=>	CLK_FAST,


  		




  
  416
  
    
		SYNC_OUT	=>	SYNC_OUT_USER


  		




  
  417
  
    
	);


  		




  
  418
  
    

  		




  
  419
  
    

  		




  
  420
  
    
	--	ChipScope Instance - Integrated Logic Analyser


  		




  
  421
  
    
	ILA_18_1024: if ILA_WIDE generate


  		




  
  422
  
    
	begin


  		




  
  423
  
    
		MyChipScopeILA: ChipScope_ILA_18_1024


  		




  
  424
  
    
		port map (


  		




  
  425
  
    
			CONTROL	=> Control2,


  		




  
  426
  
    
			CLK		=> CLK_FAST,


  		




  
  427
  
    
			DATA		=>	DataReg(17 downto 0),


  		




  
  428
  
    
			TRIG0		=>	DataReg(23 downto 0),


  		




  
  429
  
    
			TRIG_OUT	=>	TriggerOut


  		








... Этот diff ограничен, так как превышает максимальный отображаемый размер.

:@created_atf1417923072.019722C :@expires_in0