o: ActiveSupport::Cache::Entry :@compressedF: @value"8\"2\
Designs/Laboratory_instruments/AtomicCounter/VHDL/src/AtomicCounter.vhd
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architecture AtomicCounter_a of AtomicCounter is


  		




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function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is


  		




  
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function to_bcd ( bin : std_logic_vector(31 downto 0) ) return std_logic_vector is


  		




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variable i : integer:=0;


  		




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variable mybcd : std_logic_vector(19 downto 0) := (others => '0');


  		




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variable bint : std_logic_vector(15 downto 0) := bin;


  		




  
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variable mybcd : std_logic_vector(35 downto 0) := (others => '0');


  		




  
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variable bint : std_logic_vector(31 downto 0) := bin;


  		




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begin


  		




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	for i in 0 to 15 loop  -- repeating 16 times.


  		




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		mybcd(19 downto 1) := mybcd(18 downto 0);  --shifting the bits.


  		




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		mybcd(0) := bint(15);


  		




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		bint(15 downto 1) := bint(14 downto 0);


  		




  
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	for i in 0 to 31 loop  -- repeating 16 times.


  		




  
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		mybcd(35 downto 1) := mybcd(34 downto 0);  --shifting the bits.


  		




  
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		mybcd(0) := bint(31);


  		




  
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		bint(31 downto 1) := bint(30 downto 0);


  		




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		bint(0) :='0';


  		




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		if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.


  		




  
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		if(i < 31 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.


  		




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		mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);


  		




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		end if;


  		




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		if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.


  		




  
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		if(i < 31 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.


  		




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		mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);


  		




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		end if;


  		




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		if(i < 15 and mybcd(11 downto 8) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  
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		if(i < 31 and mybcd(11 downto 8) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




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		mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);


  		




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		end if;


  		




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		if(i < 15 and mybcd(15 downto 12) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  
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		if(i < 31 and mybcd(15 downto 12) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




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		mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);


  		




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		end if;


  		




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		if(i < 15 and mybcd(19 downto 16) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  
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		if(i < 31 and mybcd(19 downto 16) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




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		mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);


  		




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		end if;


  		




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		if(i < 31 and mybcd(23 downto 20) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  
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		mybcd(23 downto 20) := std_logic_vector(unsigned(mybcd(23 downto 20)) + 3);


  		




  
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		end if;


  		




  
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		if(i < 31 and mybcd(27 downto 24) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  
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		mybcd(27 downto 24) := std_logic_vector(unsigned(mybcd(27 downto 24)) + 3);


  		




  
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		end if;


  		




  
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		if(i < 31 and mybcd(31 downto 28) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  
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		mybcd(31 downto 28) := std_logic_vector(unsigned(mybcd(31 downto 28)) + 3);


  		




  
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		end if;


  		




  
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		if(i < 31 and mybcd(35 downto 32) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  
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		mybcd(35 downto 32) := std_logic_vector(unsigned(mybcd(35 downto 32)) + 3);


  		




  
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		end if;


  		




  
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	end loop;


  		




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	return mybcd;


  		




  ......




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	-- Counters


  		




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	--	----------------


  		




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	signal Counter:			unsigned(13 downto 0)	:= "00000000000000";		--	Main Counter 1 Hz, max. 9.999 kHz (binary)


  		




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	signal CounterMaxcount:	unsigned(15 downto 0)	:= "0000000000000000";	--	Main Counter 10 kHz, max. 655.35 MHz (binary)


  		




  
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	signal Counter:			unsigned(31 downto 0)	:= X"00000000";		--	Main Counter 1 Hz, max. 9.999 kHz (binary)


  		




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	--	LED Display


  		




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	--	-----------


  		




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	signal NumberPom:	std_logic_vector(35 downto 0) :=	X"000000000";					--	Variable for bin/BCD conversion


  		




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	signal Number:			std_logic_vector(35 downto 0) :=	X"000000000";				--	LED Display Input


  		




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	signal Freq:			std_logic_vector(31 downto 0) :=	X"00000000";				--	Measured Frequency


  		




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	signal MuxCounter:	unsigned(31 downto 0)	:=	(others => '0');	--	LED Multiplex - Multiplex Clock Divider


  		




  ......




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		if rising_edge(LO_CLOCK) then


  		




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			if (State = 3) or (State = 0) then


  		




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				if Counter < MAXCOUNT-1 then


  		




  
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				if DIPSW(7) = '0' then		-- Half/Full frequency


  		




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					Counter <= Counter + 1;


  		




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				else


  		




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					Counter <= (others => '0');


  		




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					CounterMaxcount <= CounterMaxcount + 1;


  		




  
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					Counter <= Counter + 2;


  		




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				end if;


  		




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			end if;


  		




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			if (State = 1) then


  		




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				Freq(15  downto 0) <= std_logic_vector("00"&Counter);


  		




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				Freq(31 downto 16) <= std_logic_vector(CounterMaxcount);


  		




  
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				Freq(31 downto 0) <= std_logic_vector(Counter);


  		




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			end if;


  		




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			if (State = 2) then


  		




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				CounterMaxcount <= (others => '0');


  		




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				Counter <= (others => '0');


  		




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			end if;


  		




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		end if;


  		




  ......




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	process (Decko)


  		




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   begin


  		




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		if falling_edge(Decko) then


  		




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			if DIPSW(7) = '0' then


  		




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				NumberPom(15  downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0);		-- Half frequency


  		




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				NumberPom(35 downto 16) <=	to_bcd(Freq(31 downto 16))(19 downto 0);


  		




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			else


  		




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				NumberPom(15  downto 0) <= to_bcd(Freq(14 downto 1)&"0")(15 downto 0);	-- Full frequency


  		




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				NumberPom(35 downto 16) <=	to_bcd(Freq(30 downto 15))(19 downto 0);


  		




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			end if;


  		




  
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			Number(35  downto 0) <= to_bcd(Freq(31 downto 0));	


  		




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		end if;


  		




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	end process;


  		




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	Number(35 downto 0) <=	NumberPom(35 downto 0);


  		




  
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--	Number(35 downto 0) <=	NumberPom(35 downto 0);


  		




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	LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar


  		




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	LED(6 downto 4) <= (others => '0');


  		












  

    
      Designs/Laboratory_instruments/AtomicCounter/VHDL/src/S3AN01B.ucf
    
  





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TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%;


  		




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NET "LO_CLOCK"	TNM_NET = LO_CLOCK;


  		




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TIMESPEC TS_LO_CLOCK = PERIOD "LO_CLOCK" 5.0 ns HIGH 50%;


  		




  
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TIMESPEC TS_LO_CLOCK = PERIOD "LO_CLOCK" 5.2 ns HIGH 50%;


  		




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# For DCM connection across the whole chip


  		




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NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE;				


  		










:@created_atf1433063302.314899'N:@expires_in0