o: ActiveSupport::Cache::Entry :@compressedF: @value""
Designs/Measuring_instruments/AtomicCounter/VHDL/AtomicCounter.xise
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    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>


  		




  175
  
  
    
    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>


  		




  176
  
  
    
    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>


  		




  177
  
  
    
    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>


  		




  178
  
  
    
    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>


  		




  179
  
  
    
    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>


  		




  180
  
  
    
    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>


  		




  181
  
  
    
    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>


  		




  182
  
  
    
    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  183
  
  
    
    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>


  		




  184
  
  
    
    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>


  		




  185
  
  
    
    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>


  		




  186
  
  
    
    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>


  		




  187
  
  
    
    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>


  		




  188
  
  
    
    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>


  		




  189
  
  
    
    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>


  		




  190
  
  
    
    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>


  		




  191
  
  
    
    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>


  		




  192
  
  
    
    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>


  		




  193
  
  
    
    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>


  		




  194
  
  
    
    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>


  		




  195
  
  
    
    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>


  		




  196
  
  
    
    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>


  		




  197
  
  
    
    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>


  		




  198
  
  
    
    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>


  		




  199
  
  
    
    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>


  		




  200
  
  
    
    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  201
  
  
    
    <property xil_pn:name="Output File Name" xil_pn:value="AtomicCounter" xil_pn:valueState="default"/>


  		




  202
  
  
    
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  203
  
  
    
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>


  		




  204
  
  
    
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>


  		




  205
  
  
    
    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>


  		




  206
  
  
    
    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  207
  
  
    
    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  208
  
  
    
    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  209
  
  
    
    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>


  		




  210
  
  
    
    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>


  		




  211
  
  
    
    <property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  212
  
  
    
    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>


  		




  213
  
  
    
    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>


  		




  214
  
  
    
    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomicCounter_map.vhd" xil_pn:valueState="default"/>


  		




  215
  
  
    
    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomicCounter_timesim.vhd" xil_pn:valueState="default"/>


  		




  216
  
  
    
    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomicCounter_synthesis.vhd" xil_pn:valueState="default"/>


  		




  217
  
  
    
    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomicCounter_translate.vhd" xil_pn:valueState="default"/>


  		




  218
  
  
    
    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  219
  
  
    
    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  220
  
  
    
    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>


  		




  221
  
  
    
    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>


  		




  222
  
  
    
    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  223
  
  
    
    <property xil_pn:name="Project Description" xil_pn:value="A Counter synchronised by GPS." xil_pn:valueState="non-default"/>


  		




  224
  
  
    
    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>


  		




  225
  
  
    
    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>


  		




  226
  
  
    
    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  227
  
  
    
    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>


  		




  228
  
  
    
    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  229
  
  
    
    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>


  		




  230
  
  
    
    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  231
  
  
    
    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>


  		




  232
  
  
    
    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>


  		




  233
  
  
    
    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>


  		




  234
  
  
    
    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  235
  
  
    
    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>


  		




  236
  
  
    
    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>


  		




  237
  
  
    
    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>


  		




  238
  
  
    
    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomicCounter" xil_pn:valueState="default"/>


  		




  239
  
  
    
    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>


  		




  240
  
  
    
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  241
  
  
    
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  242
  
  
    
    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>


  		




  243
  
  
    
    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>


  		




  244
  
  
    
    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>


  		




  245
  
  
    
    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>


  		




  246
  
  
    
    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>


  		




  247
  
  
    
    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>


  		




  248
  
  
    
    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>


  		




  249
  
  
    
    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  250
  
  
    
    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  251
  
  
    
    <property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  252
  
  
    
    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>


  		




  253
  
  
    
    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  254
  
  
    
    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  255
  
  
    
    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  256
  
  
    
    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  257
  
  
    
    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  258
  
  
    
    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>


  		




  259
  
  
    
    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>


  		




  260
  
  
    
    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>


  		




  261
  
  
    
    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>


  		




  262
  
  
    
    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>


  		




  263
  
  
    
    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>


  		




  264
  
  
    
    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>


  		




  265
  
  
    
    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  266
  
  
    
    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  267
  
  
    
    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>


  		




  268
  
  
    
    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>


  		




  269
  
  
    
    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>


  		




  270
  
  
    
    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>


  		




  271
  
  
    
    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>


  		




  272
  
  
    
    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>


  		




  273
  
  
    
    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  274
  
  
    
    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>


  		




  275
  
  
    
    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>


  		




  276
  
  
    
    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>


  		




  277
  
  
    
    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>


  		




  278
  
  
    
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>


  		




  279
  
  
    
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>


  		




  280
  
  
    
    <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>


  		




  281
  
  
    
    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>


  		




  282
  
  
    
    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>


  		




  283
  
  
    
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>


  		




  284
  
  
    
    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>


  		




  285
  
  
    
    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>


  		




  286
  
  
    
    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>


  		




  287
  
  
    
    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>


  		




  288
  
  
    
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>


  		




  289
  
  
    
    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  290
  
  
    
    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>


  		




  291
  
  
    
    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>


  		




  292
  
  
    
    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  293
  
  
    
    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>


  		




  294
  
  
    
    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  295
  
  
    
    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  296
  
  
    
    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  297
  
  
    
    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  298
  
  
    
    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  299
  
  
    
    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  300
  
  
    
    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  301
  
  
    
    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  302
  
  
    
    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  303
  
  
    
    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  304
  
  
    
    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  305
  
  
    
    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  306
  
  
    
    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  307
  
  
    
    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>


  		




  308
  
  
    
    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  309
  
  
    
    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>


  		




  310
  
  
    
    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>


  		




  311
  
  
    
    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  312
  
  
    
    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/13.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>


  		




  313
  
  
    
    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>


  		




  314
  
  
    
    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>


  		




  315
  
  
    
    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  316
  
  
    
    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  317
  
  
    
    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>


  		




  318
  
  
    
    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>


  		




  319
  
  
    
    <property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>


  		




  320
  
  
    
    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>


  		




  321
  
  
    
    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>


  		




  322
  
  
    
    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>


  		




  323
  
  
    
    <!--                                                                                  -->


  		




  324
  
  
    
    <!-- The following properties are for internal use only. These should not be modified.-->


  		




  325
  
  
    
    <!--                                                                                  -->


  		




  326
  
  
    
    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>


  		




  327
  
  
    
    <property xil_pn:name="PROP_DesignName" xil_pn:value="gtime" xil_pn:valueState="non-default"/>


  		




  328
  
  
    
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>


  		




  329
  
  
    
    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>


  		




  330
  
  
    
    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>


  		




  331
  
  
    
    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>


  		




  332
  
  
    
    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>


  		




  333
  
  
    
    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>


  		




  334
  
  
    
    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>


  		




  335
  
  
    
    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>


  		




  336
  
  
    
    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-08-28T23:51:54" xil_pn:valueState="non-default"/>


  		




  337
  
  
    
    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AAC6D7E01D414DD992A4DDE7C0B857EB" xil_pn:valueState="non-default"/>


  		




  338
  
  
    
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>


  		




  339
  
  
    
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>


  		




  340
  
  
    
  </properties>


  		




  341
  
  
    

  		




  342
  
  
    
  <bindings/>


  		




  343
  
  
    

  		




  344
  
  
    
  <libraries/>


  		




  345
  
  
    

  		




  346
  
  
    
</project>


  		












  

    
      Designs/Measuring_instruments/AtomicCounter/VHDL/AtomicCounter.prj
    
  





  1
  
  
    
vhdl work "src/AtomicCounter.vhd"


  		












  

    
      Designs/Measuring_instruments/AtomicCounter/VHDL/src/S3AN01B.ucf
    
  





  1
  
  
    
# Board:		www.mlab.cz S3AN01A


  		




  2
  
  
    
# Device:	XC3S50AN-4C


  		




  3
  
  
    
# Setting:	Generate Programming File / Startup Options / Drive Done Pin High: yes


  		




  4
  
  
    
# Main Clock (Embedded 100MHz board oscillator)


  		




  5
  
  
    
NET "CLK100MHz"	LOC = P60  |IOSTANDARD = LVCMOS33;


  		




  6
  
  
    
#NET "CLK100MHz"	LOC = P125 | IOSTANDARD = LVCMOS33;


  		




  7
  
  
    

  		




  8
  
  
    
NET "CLK100MHz"	TNM_NET = CLK100MHz;


  		




  9
  
  
    
TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%;


  		




  10
  
  
    

  		




  11
  
  
    
NET "LO_CLOCK"	TNM_NET = LO_CLOCK;


  		




  12
  
  
    
TIMESPEC TS_LO_CLOCK = PERIOD "LO_CLOCK" 5.2 ns HIGH 50%;


  		




  13
  
  
    

  		




  14
  
  
    
# For DCM connection across the whole chip


  		




  15
  
  
    
NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE;				


  		




  16
  
  
    
NET "PS2_CLK2"  CLOCK_DEDICATED_ROUTE = FALSE;


  		




  17
  
  
    

  		




  18
  
  
    
# Mode signals


  		




  19
  
  
    
NET "M[0]"			LOC = P38  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  20
  
  
    
NET "M[1]"			LOC = P37  |IOSTANDARD = LVCMOS33 |PULLUP = YES;		# Use jumper on M1 and M2 for boot from external SPI Flash Memory


  		




  21
  
  
    
NET "M[2]"			LOC = P39  |IOSTANDARD = LVCMOS33 |PULLUP = YES;		# Use jumper on M2 for boot from internal Flash memory


  		




  22
  
  
    
# SPI Flash Vendor Mode Select (for external SPI boot Flash)


  		




  23
  
  
    
NET "VS[0]"			LOC = P45  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  24
  
  
    
NET "VS[1]"			LOC = P44  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  25
  
  
    
NET "VS[2]"			LOC = P43  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  26
  
  
    

  		




  27
  
  
    
# DIP Switches (positive signals with pull-down)


  		




  28
  
  
    
NET "DIPSW[0]"		LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  29
  
  
    
NET "DIPSW[1]"		LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  30
  
  
    
NET "DIPSW[2]"		LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  31
  
  
    
NET "DIPSW[3]"		LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  32
  
  
    
NET "DIPSW[4]"		LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  33
  
  
    
NET "DIPSW[5]"		LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  34
  
  
    
NET "DIPSW[6]"		LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  35
  
  
    
NET "DIPSW[7]"		LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  36
  
  
    

  		




  37
  
  
    
# Push Buttons (positive signals with pull-down)


  		




  38
  
  
    
NET "PB[0]"			LOC = P121 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  39
  
  
    
NET "PB[1]"			LOC = P120 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  40
  
  
    
NET "PB[2]"			LOC = P117 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  41
  
  
    
NET "PB[3]"			LOC = P116 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  42
  
  
    

  		




  43
  
  
    
# LED String (positive output signals)


  		




  44
  
  
    
NET "LED[0]"		LOC = P64  |IOSTANDARD = LVCMOS33;


  		




  45
  
  
    
NET "LED[1]"		LOC = P63  |IOSTANDARD = LVCMOS33;


  		




  46
  
  
    
NET "LED[2]"		LOC = P51  |IOSTANDARD = LVCMOS33;


  		




  47
  
  
    
NET "LED[3]"		LOC = P50  |IOSTANDARD = LVCMOS33;


  		




  48
  
  
    
NET "LED[4]"		LOC = P49  |IOSTANDARD = LVCMOS33;


  		




  49
  
  
    
NET "LED[5]"		LOC = P48  |IOSTANDARD = LVCMOS33;


  		




  50
  
  
    
NET "LED[6]"		LOC = P47  |IOSTANDARD = LVCMOS33;


  		




  51
  
  
    
NET "LED[7]"		LOC = P46  |IOSTANDARD = LVCMOS33;


  		




  52
  
  
    

  		




  53
  
  
    
# LED Display Output Signals (negative, multiplexed)


  		




  54
  
  
    
NET "LD_A_n"		LOC = P15  |IOSTANDARD = LVCMOS33;


  		




  55
  
  
    
NET "LD_B_n"		LOC = P30  |IOSTANDARD = LVCMOS33;


  		




  56
  
  
    
NET "LD_C_n"		LOC = P21  |IOSTANDARD = LVCMOS33;


  		




  57
  
  
    
NET "LD_D_n"		LOC = P19  |IOSTANDARD = LVCMOS33;


  		




  58
  
  
    
NET "LD_E_n"		LOC = P18  |IOSTANDARD = LVCMOS33;


  		




  59
  
  
    
NET "LD_F_n"		LOC = P16  |IOSTANDARD = LVCMOS33;


  		




  60
  
  
    
NET "LD_G_n"		LOC = P24  |IOSTANDARD = LVCMOS33;


  		




  61
  
  
    
NET "LD_DP_n"		LOC = P20  |IOSTANDARD = LVCMOS33;


  		




  62
  
  
    

  		




  63
  
  
    
NET "LD_0_n"		LOC = P25  |IOSTANDARD = LVCMOS33;


  		




  64
  
  
    
NET "LD_1_n"		LOC = P31  |IOSTANDARD = LVCMOS33;


  		




  65
  
  
    
NET "LD_2_n"		LOC = P32  |IOSTANDARD = LVCMOS33;


  		




  66
  
  
    
NET "LD_3_n"		LOC = P13  |IOSTANDARD = LVCMOS33;		# !!! Connect U1.13 with U1.33


  		




  67
  
  
    
NET "LD_4_n"		LOC = P27  |IOSTANDARD = LVCMOS33;


  		




  68
  
  
    
NET "LD_5_n"		LOC = P29  |IOSTANDARD = LVCMOS33;


  		




  69
  
  
    
NET "LD_6_n"		LOC = P28  |IOSTANDARD = LVCMOS33;


  		




  70
  
  
    
NET "LD_7_n"		LOC = P12  |IOSTANDARD = LVCMOS33;		# !!! Connect U1.12 with U1.35


  		




  71
  
  
    
# VGA Analog Display Connection (outputs)


  		




  72
  
  
    
NET "VGA_R[0]"		LOC = P3   |IOSTANDARD = LVCMOS33;


  		




  73
  
  
    
NET "VGA_R[1]"		LOC = P4   |IOSTANDARD = LVCMOS33;


  		




  74
  
  
    
NET "VGA_G[0]"		LOC = P5   |IOSTANDARD = LVCMOS33;


  		




  75
  
  
    
NET "VGA_G[1]"		LOC = P6   |IOSTANDARD = LVCMOS33;


  		




  76
  
  
    
NET "VGA_B[0]"		LOC = P7   |IOSTANDARD = LVCMOS33;


  		




  77
  
  
    
NET "VGA_B[1]"		LOC = P8   |IOSTANDARD = LVCMOS33;


  		




  78
  
  
    
NET "VGA_VS"		LOC = P10  |IOSTANDARD = LVCMOS33;


  		




  79
  
  
    
NET "VGA_HS"		LOC = P11  |IOSTANDARD = LVCMOS33;


  		




  80
  
  
    

  		




  81
  
  
    
# Bank 1 Port (input for tests, pull-up)


  		




  82
  
  
    
NET "B[0]"			LOC = P75  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  83
  
  
    
NET "B[1]"			LOC = P76  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  84
  
  
    
NET "B[2]"			LOC = P77  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  85
  
  
    
NET "B[3]"			LOC = P78  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  86
  
  
    
NET "B[4]"			LOC = P82  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  87
  
  
    
NET "B[5]"			LOC = P83  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  88
  
  
    
NET "B[6]"			LOC = P84  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  89
  
  
    
NET "B[7]"			LOC = P85  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  90
  
  
    
NET "B[8]"			LOC = P87  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  91
  
  
    
NET "B[9]"			LOC = P88  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  92
  
  
    
NET "B[10]"			LOC = P90  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  93
  
  
    
NET "B[11]"			LOC = P91  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  94
  
  
    
NET "B[12]"			LOC = P92  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  95
  
  
    
NET "B[13]"			LOC = P93  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  96
  
  
    
NET "B[14]"			LOC = P96  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  97
  
  
    
NET "B[15]"			LOC = P98  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  98
  
  
    
NET "B[16]"			LOC = P99  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  99
  
  
    
NET "B[17]"			LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  100
  
  
    
NET "B[18]"			LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  101
  
  
    
NET "B[19]"			LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  102
  
  
    
NET "B[20]"			LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  103
  
  
    
NET "B[21]"			LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  104
  
  
    
NET "B[22]"			LOC = P79  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  105
  
  
    
NET "B[23]"			LOC = P80  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  106
  
  
    
NET "B[24]"			LOC = P97  |IOSTANDARD = LVCMOS33 |PULLUP = YES;		# Connected with B[23] on PCB


  		




  107
  
  
    
# PS/2 Bidirectional Port (open collector, J31 and J32)


  		




  108
  
  
    
#NET "PS2_CLK1"	LOC = P    | IOSTANDARD = LVCMOS33 | PULLUP = YES;		# S3AN01A PCB Design has bug so these pins


  		




  109
  
  
    
#NET "PS2_DATA1"	LOC = P    | IOSTANDARD = LVCMOS33 | PULLUP = YES;		# will be assinged after PCB redesign


  		




  110
  
  
    
NET "PS2_CLK2"		LOC = P42  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  111
  
  
    
NET "PS2_DATA2"	LOC = P58  |IOSTANDARD = LVCMOS33 |PULLUP = YES;


  		




  112
  
  
    

  		




  113
  
  
    
# Diferencial Signals on 4 pin header (J7)


  		




  114
  
  
    
NET "DIF1P"			LOC = P110 |IOSTANDARD = LVCMOS33 ;


  		




  115
  
  
    
NET "DIF1N"			LOC = P111 |IOSTANDARD = LVCMOS33 ;


  		




  116
  
  
    
NET "DIF2P"			LOC = P112 |IOSTANDARD = LVCMOS33 ;


  		




  117
  
  
    
NET "DIF2N"			LOC = P113 |IOSTANDARD = LVCMOS33 ;


  		




  118
  
  
    

  		




  119
  
  
    
# I2C Signals (on connector J30)


  		




  120
  
  
    
NET "I2C_SCL"		LOC = P115 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  121
  
  
    
NET "I2C_SDA"		LOC = P114 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  122
  
  
    

  		




  123
  
  
    
# Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)


  		




  124
  
  
    
NET "SD1AP"			LOC = P54  |IOSTANDARD = LVPECL_33;


  		




  125
  
  
    
NET "SD1AN"			LOC = P55  |IOSTANDARD = LVPECL_33; 


  		




  126
  
  
    
NET "SD1BP"			LOC = P59  |IOSTANDARD = LVCMOS33 ;


  		




  127
  
  
    
NET "SD1BN"			LOC = P57  |IOSTANDARD = LVCMOS33 ;


  		




  128
  
  
    
NET "SD2AP"			LOC = P124 |IOSTANDARD = LVDS_33 ;


  		




  129
  
  
    
NET "SD2AN"			LOC = P126 |IOSTANDARD = LVDS_33 ;


  		




  130
  
  
    
NET "SD2BP"			LOC = P131 |IOSTANDARD = LVCMOS33 ;


  		




  131
  
  
    
NET "SD2BN"			LOC = P129 |IOSTANDARD = LVCMOS33 ;


  		




  132
  
  
    

  		




  133
  
  
    
# SPI Memory Interface


  		




  134
  
  
    
NET "SPI_CS_n"		LOC = P41  |IOSTANDARD = LVCMOS33 |PULLUP   = YES;


  		




  135
  
  
    
NET "SPI_DO"		LOC = P71  |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  136
  
  
    
NET "SPI_DI"		LOC = P62  |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  137
  
  
    
NET "SPI_CLK"		LOC = P72  |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  138
  
  
    
NET "SPI_WP_n"		LOC = P70  |IOSTANDARD = LVCMOS33 |PULLUP   = YES;


  		




  139
  
  
    

  		




  140
  
  
    
# Analog In Out


  		




  141
  
  
    
NET "ANA_OUTD"		LOC = P67  |IOSTANDARD = LVCMOS33;


  		




  142
  
  
    
NET "ANA_REFD"		LOC = P68  |IOSTANDARD = LVCMOS33;


  		




  143
  
  
    
NET "ANA_IND"		LOC = P69  |IOSTANDARD = LVCMOS33 |PULLDOWN = YES;


  		




  144
  
  
    

  		




  145
  
  
    
/*


  		




  146
  
  
    
# Used Signals (test points)


  		




  147
  
  
    
NET "TPS1"			LOC = P53  | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;


  		




  148
  
  
    
NET "TPS2"			LOC = P125 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;


  		




  149
  
  
    
NET "TPS3"			LOC = P127 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;


  		




  150
  
  
    
NET "TPS4"			LOC = P130 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;


  		




  151
  
  
    
NET "TPS5"			LOC = P141 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;


  		




  152
  
  
    
NET "TPS6"			LOC = P123 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;


  		




  153
  
  
    
NET "XXX1"			LOC = P33  | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;		# input only


  		




  154
  
  
    
NET "XXX2"			LOC = P35  | IOSTANDARD = LVCMOS33 | PULLDOWN = YES;		# input only


  		




  155
  
  
    
*/


  		












  

    
      Designs/Measuring_instruments/AtomicCounter/VHDL/src/AtomicCounter.vhd
    
  





  1
  
  
    
----------------------------------------------------------------------------------


  		




  2
  
  
    
-- Company:        www.mlab.cz


  		




  3
  
  
    
-- Based on code written by MIHO.


  		




  4
  
  
    
-- 


  		




  5
  
  
    
-- HW Design Name: S3AN01A


  		




  6
  
  
    
-- Project Name:   Atomic Counter


  		




  7
  
  
    
-- Target Devices: XC3S50AN-4


  		




  8
  
  
    
-- Tool versions:  ISE 13.3


  		




  9
  
  
    
-- Description:   Counter up to 640 MHz synchonised by GPS.


  		




  10
  
  
    
--						Output frequency is displayed on the 7seg. LED display.


  		




  11
  
  
    
--						You can choice half or full frequency by DIPSW7.	


  		




  12
  
  
    
--


  		




  13
  
  
    
-- Dependencies:   TTLPECL01A, GPS01A


  		




  14
  
  
    
--


  		




  15
  
  
    
-- Version:  $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $


  		




  16
  
  
    
--


  		




  17
  
  
    
----------------------------------------------------------------------------------


  		




  18
  
  
    

  		




  19
  
  
    
library IEEE;


  		




  20
  
  
    
use IEEE.STD_LOGIC_1164.ALL;


  		




  21
  
  
    
use IEEE.numeric_std.ALL;


  		




  22
  
  
    

  		




  23
  
  
    
library UNISIM;


  		




  24
  
  
    
use UNISIM.vcomponents.all;


  		




  25
  
  
    

  		




  26
  
  
    
entity AtomicCounter is


  		




  27
  
  
    
	generic (


  		




  28
  
  
    
		--	Top Value for 100MHz Clock Counter


  		




  29
  
  
    
		MAXCOUNT:	integer	:=	10_000;				-- Maximum for the first counter


  		




  30
  
  
    
		MUXCOUNT:	integer	:=	100_000				--	LED Display Multiplex Clock Divider


  		




  31
  
  
    
	);


  		




  32
  
  
    
	port (


  		




  33
  
  
    
		-- Clock on PCB


  		




  34
  
  
    
		CLK100MHz:	in		std_logic;


  		




  35
  
  
    

  		




  36
  
  
    
		-- Mode Signals (usualy not used)


  		




  37
  
  
    
		M:				in		std_logic_vector(2 downto 0);


  		




  38
  
  
    
		VS:			in		std_logic_vector(2 downto 0);


  		




  39
  
  
    

  		




  40
  
  
    
		-- Dipswitch Inputs


  		




  41
  
  
    
		DIPSW:		in		std_logic_vector(7 downto 0);


  		




  42
  
  
    

  		




  43
  
  
    
		-- Push Buttons


  		




  44
  
  
    
		PB:			in		std_logic_vector(3 downto 0);


  		




  45
  
  
    

  		




  46
  
  
    
		-- LED Bar Outputs


  		




  47
  
  
    
		LED:			out	std_logic_vector(7 downto 0);


  		




  48
  
  
    

  		




  49
  
  
    
		--	LED Display (8 digit with 7 segments and ddecimal point)


  		




  50
  
  
    
		LD_A_n:		out	std_logic;


  		




  51
  
  
    
		LD_B_n:		out	std_logic;


  		




  52
  
  
    
		LD_C_n:		out	std_logic;


  		




  53
  
  
    
		LD_D_n:		out	std_logic;


  		




  54
  
  
    
		LD_E_n:		out	std_logic;


  		




  55
  
  
    
		LD_F_n:		out	std_logic;


  		




  56
  
  
    
		LD_G_n:		out	std_logic;


  		




  57
  
  
    
		LD_DP_n:		out	std_logic;


  		




  58
  
  
    
		LD_0_n:		out	std_logic;


  		




  59
  
  
    
		LD_1_n:		out	std_logic;


  		




  60
  
  
    
		LD_2_n:		out	std_logic;


  		




  61
  
  
    
		LD_3_n:		out	std_logic;


  		




  62
  
  
    
		LD_4_n:		out	std_logic;


  		




  63
  
  
    
		LD_5_n:		out	std_logic;


  		




  64
  
  
    
		LD_6_n:		out	std_logic;


  		




  65
  
  
    
		LD_7_n:		out	std_logic;


  		




  66
  
  
    

  		




  67
  
  
    
		--	VGA Video Out Port


  		




  68
  
  
    
		VGA_R:		out	std_logic_vector(1 downto 0);


  		




  69
  
  
    
		VGA_G:		out	std_logic_vector(1 downto 0);


  		




  70
  
  
    
		VGA_B:		out	std_logic_vector(1 downto 0);


  		




  71
  
  
    
		VGA_VS:		out	std_logic;


  		




  72
  
  
    
		VGA_HS:		out	std_logic;


  		




  73
  
  
    

  		




  74
  
  
    
		-- Bank 1 Pins - Inputs for this Test


  		




  75
  
  
    
		B:				inout		std_logic_vector(24 downto 0);


  		




  76
  
  
    
		


  		




  77
  
  
    
		-- PS/2 Bidirectional Port (open collector, J31 and J32)


  		




  78
  
  
    
		PS2_CLK1:	inout	std_logic;


  		




  79
  
  
    
		PS2_DATA1:	inout	std_logic;


  		




  80
  
  
    
		PS2_CLK2:	inout	std_logic;


  		




  81
  
  
    
		PS2_DATA2:	inout	std_logic;


  		




  82
  
  
    

  		




  83
  
  
    
		--	Diferencial Signals on 4 pin header (J7)


  		




  84
  
  
    
		DIF1P:		inout	std_logic;


  		




  85
  
  
    
		DIF1N:		inout	std_logic;


  		




  86
  
  
    
		DIF2P:		inout	std_logic;


  		




  87
  
  
    
		DIF2N:		inout	std_logic;


  		




  88
  
  
    
		


  		




  89
  
  
    

  		




  90
  
  
    
		--	I2C Signals (on connector J30)


  		




  91
  
  
    
		I2C_SCL:		inout	std_logic;


  		




  92
  
  
    
		I2C_SDA:		inout	std_logic;


  		




  93
  
  
    

  		




  94
  
  
    
		--	Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)


  		




  95
  
  
    
		SD1AP:		inout	std_logic;


  		




  96
  
  
    
		SD1AN:		inout	std_logic;


  		




  97
  
  
    
		SD1BP:		inout	std_logic;


  		




  98
  
  
    
		SD1BN:		inout	std_logic;


  		




  99
  
  
    
		SD2AP:		inout	std_logic;


  		




  100
  
  
    
		SD2AN:		inout	std_logic;


  		




  101
  
  
    
		SD2BP:		inout	std_logic;


  		




  102
  
  
    
		SD2BN:		inout	std_logic;


  		




  103
  
  
    

  		




  104
  
  
    
		--	Analog In Out


  		




  105
  
  
    
	   ANA_OUTD:	out	std_logic;


  		




  106
  
  
    
		ANA_REFD:	out	std_logic;


  		




  107
  
  
    
		ANA_IND:		in		std_logic;


  		




  108
  
  
    

  		




  109
  
  
    
		--	SPI Memory Interface


  		




  110
  
  
    
		SPI_CS_n:	inout	std_logic;


  		




  111
  
  
    
		SPI_DO:		inout	std_logic;


  		




  112
  
  
    
		SPI_DI:		inout	std_logic;


  		




  113
  
  
    
		SPI_CLK:		inout	std_logic;


  		




  114
  
  
    
		SPI_WP_n:	inout	std_logic


  		




  115
  
  
    
	);


  		




  116
  
  
    
end entity AtomicCounter;


  		




  117
  
  
    

  		




  118
  
  
    

  		




  119
  
  
    
architecture AtomicCounter_a of AtomicCounter is


  		




  120
  
  
    

  		




  121
  
  
    
function to_bcd ( bin : std_logic_vector(31 downto 0) ) return std_logic_vector is


  		




  122
  
  
    
variable i : integer:=0;


  		




  123
  
  
    
variable mybcd : std_logic_vector(35 downto 0) := (others => '0');


  		




  124
  
  
    
variable bint : std_logic_vector(31 downto 0) := bin;


  		




  125
  
  
    
begin


  		




  126
  
  
    
	for i in 0 to 31 loop  -- repeating 16 times.


  		




  127
  
  
    
		mybcd(35 downto 1) := mybcd(34 downto 0);  --shifting the bits.


  		




  128
  
  
    
		mybcd(0) := bint(31);


  		




  129
  
  
    
		bint(31 downto 1) := bint(30 downto 0);


  		




  130
  
  
    
		bint(0) :='0';


  		




  131
  
  
    

  		




  132
  
  
    

  		




  133
  
  
    
		if(i < 31 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.


  		




  134
  
  
    
		mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);


  		




  135
  
  
    
		end if;


  		




  136
  
  
    

  		




  137
  
  
    
		if(i < 31 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.


  		




  138
  
  
    
		mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);


  		




  139
  
  
    
		end if;


  		




  140
  
  
    

  		




  141
  
  
    
		if(i < 31 and mybcd(11 downto 8) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  142
  
  
    
		mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);


  		




  143
  
  
    
		end if;


  		




  144
  
  
    

  		




  145
  
  
    
		if(i < 31 and mybcd(15 downto 12) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  146
  
  
    
		mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);


  		




  147
  
  
    
		end if;


  		




  148
  
  
    

  		




  149
  
  
    
		if(i < 31 and mybcd(19 downto 16) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  150
  
  
    
		mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);


  		




  151
  
  
    
		end if;


  		




  152
  
  
    

  		




  153
  
  
    
		if(i < 31 and mybcd(23 downto 20) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  154
  
  
    
		mybcd(23 downto 20) := std_logic_vector(unsigned(mybcd(23 downto 20)) + 3);


  		




  155
  
  
    
		end if;


  		




  156
  
  
    

  		




  157
  
  
    
		if(i < 31 and mybcd(27 downto 24) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  158
  
  
    
		mybcd(27 downto 24) := std_logic_vector(unsigned(mybcd(27 downto 24)) + 3);


  		




  159
  
  
    
		end if;


  		




  160
  
  
    

  		




  161
  
  
    
		if(i < 31 and mybcd(31 downto 28) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  162
  
  
    
		mybcd(31 downto 28) := std_logic_vector(unsigned(mybcd(31 downto 28)) + 3);


  		




  163
  
  
    
		end if;


  		




  164
  
  
    

  		




  165
  
  
    
		if(i < 31 and mybcd(35 downto 32) > "0100") then  --add 3 if BCD digit is greater than 4.


  		




  166
  
  
    
		mybcd(35 downto 32) := std_logic_vector(unsigned(mybcd(35 downto 32)) + 3);


  		




  167
  
  
    
		end if;


  		




  168
  
  
    

  		




  169
  
  
    
	end loop;


  		




  170
  
  
    
	


  		




  171
  
  
    
	return mybcd;


  		




  172
  
  
    
end to_bcd;


  		




  173
  
  
    

  		




  174
  
  
    

  		




  175
  
  
    
	-- Counters


  		




  176
  
  
    
	--	----------------


  		




  177
  
  
    

  		




  178
  
  
    
	signal Counter:			unsigned(31 downto 0)	:= X"00000000";		--	Main Counter 1 Hz, max. 9.999 kHz (binary)


  		




  179
  
  
    

  		




  180
  
  
    

  		




  181
  
  
    
	--	LED Display


  		




  182
  
  
    
	--	-----------


  		




  183
  
  
    

  		




  184
  
  
    
	signal Number:			std_logic_vector(35 downto 0) :=	X"000000000";				--	LED Display Input


  		




  185
  
  
    
	signal Freq:			std_logic_vector(31 downto 0) :=	X"00000000";				--	Measured Frequency


  		




  186
  
  
    
	signal MuxCounter:	unsigned(31 downto 0)	:=	(others => '0');	--	LED Multiplex - Multiplex Clock Divider


  		




  187
  
  
    
	signal Enable:			std_logic;


  		




  188
  
  
    
	signal Digits:			std_logic_vector(7 downto 0)	:=	X"01";	--	LED Multiplex - Digit Counter - LED Digit Output


  		




  189
  
  
    
	signal Segments:		std_logic_vector(0 to 7);						--	LED Segment Output


  		




  190
  
  
    
	signal Code:			std_logic_vector(3 downto 0);					--	BCD to 7 Segment Decoder Output


  		




  191
  
  
    

  		




  192
  
  
    
	


  		




  193
  
  
    
	signal LO_CLOCK:	std_logic;		-- Frequency divided by 2


  		




  194
  
  
    
	signal EXT_CLOCK:	std_logic;		-- Input Frequency


  		




  195
  
  
    

  		




  196
  
  
    
	signal Decko:	std_logic;												-- D flip-flop


  		




  197
  
  
    
	signal State:	unsigned(2 downto 0)	:=	(others => '0');		-- Inner states of automata


  		




  198
  
  
    
 	


  		




  199
  
  
    
begin


  		




  200
  
  
    

  		




  201
  
  
    
	-- Input divider by 2


  		




  202
  
  
    
	process (EXT_CLOCK)


  		




  203
  
  
    
	begin


  		




  204
  
  
    
		if rising_edge(EXT_CLOCK) then


  		




  205
  
  
    
			LO_CLOCK <= not LO_CLOCK;


  		




  206
  
  
    
		end if;


  		




  207
  
  
    
	end process;


  		




  208
  
  
    

  		




  209
  
  
    

  		




  210
  
  
    
	-- Counter


  		




  211
  
  
    
	process (LO_CLOCK)


  		




  212
  
  
    
	begin


  		




  213
  
  
    
	


  		




  214
  
  
    
		if rising_edge(LO_CLOCK) then


  		




  215
  
  
    
		


  		




  216
  
  
    
			if (State = 3) or (State = 0) then


  		




  217
  
  
    
				if DIPSW(7) = '0' then		-- Half/Full frequency


  		




  218
  
  
    
					Counter <= Counter + 1;


  		




  219
  
  
    
				else


  		




  220
  
  
    
					Counter <= Counter + 2;


  		




  221
  
  
    
				end if;


  		




  222
  
  
    
			end if;


  		




  223
  
  
    
			if (State = 1) then


  		




  224
  
  
    
				Freq(31 downto 0) <= std_logic_vector(Counter);


  		




  225
  
  
    
			end if;


  		




  226
  
  
    
			if (State = 2) then


  		




  227
  
  
    
				Counter <= (others => '0');


  		




  228
  
  
    
			end if;


  		




  229
  
  
    
		end if;


  		




  230
  
  
    

  		




  231
  
  
    
	end process;	


  		




  232
  
  
    

  		




  233
  
  
    

  		




  234
  
  
    
	-- Sampling 1PPS signal


  		




  235
  
  
    
	process (LO_CLOCK)


  		




  236
  
  
    
	begin


  		




  237
  
  
    
		if rising_edge(LO_CLOCK) then


  		




  238
  
  
    
			Decko <= B(22);


  		




  239
  
  
    
		end if;


  		




  240
  
  
    
	end process;


  		




  241
  
  
    

  		




  242
  
  
    
	-- Automata for controlling the Counter


  		




  243
  
  
    
	process (LO_CLOCK)


  		




  244
  
  
    
	begin


  		




  245
  
  
    
		if rising_edge(LO_CLOCK) then


  		




  246
  
  
    
			if (Decko = '1') then


  		




  247
  
  
    
				if (State < 3) then


  		




  248
  
  
    
					State <= State + 1;


  		




  249
  
  
    
				end if;


  		




  250
  
  
    
			else


  		




  251
  
  
    
				State <= (others => '0');


  		




  252
  
  
    
			end if;


  		




  253
  
  
    
		end if;


  		




  254
  
  
    
	end process;


  		




  255
  
  
    

  		




  256
  
  
    
	-- Coding to BCD for LED Display 


  		




  257
  
  
    

  		




  258
  
  
    
	process (Decko)


  		




  259
  
  
    
   begin


  		




  260
  
  
    
		if falling_edge(Decko) then


  		




  261
  
  
    
			Number(35  downto 0) <= to_bcd(Freq(31 downto 0));	


  		




  262
  
  
    
		end if;


  		




  263
  
  
    
	end process;


  		




  264
  
  
    

  		




  265
  
  
    
--	Number(35 downto 0) <=	NumberPom(35 downto 0);


  		




  266
  
  
    
	


  		




  267
  
  
    
	LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar


  		




  268
  
  
    
	LED(6 downto 4) <= (others => '0');


  		




  269
  
  
    
	LED(3 downto 0) <= Number(35 downto 32); --	Disply 100-th of MHz on LEDbar


  		




  270
  
  
    

  		




  271
  
  
    
	--	LED Display (multiplexed)


  		




  272
  
  
    
	--	=========================


  		




  273
  
  
    

  		




  274
  
  
    
	--	Connect LED Display Output Ports (negative outputs)


  		




  275
  
  
    
	LD_A_n	<=	not (Segments(0) and Enable);


  		




  276
  
  
    
	LD_B_n	<=	not (Segments(1) and Enable);


  		




  277
  
  
    
	LD_C_n	<=	not (Segments(2) and Enable);


  		




  278
  
  
    
	LD_D_n	<=	not (Segments(3) and Enable);


  		




  279
  
  
    
	LD_E_n	<=	not (Segments(4) and Enable);


  		




  280
  
  
    
	LD_F_n	<=	not (Segments(5) and Enable);


  		




  281
  
  
    
	LD_G_n	<=	not (Segments(6) and Enable);


  		




  282
  
  
    
	LD_DP_n	<=	not (Segments(7) and Enable);


  		




  283
  
  
    

  		




  284
  
  
    
	LD_0_n	<=	not Digits(0);


  		




  285
  
  
    
	LD_1_n	<=	not Digits(1);


  		




  286
  
  
    
	LD_2_n	<=	not Digits(2);


  		




  287
  
  
    
	LD_3_n	<=	not Digits(3);


  		




  288
  
  
    
	LD_4_n	<=	not Digits(4);


  		




  289
  
  
    
	LD_5_n	<=	not Digits(5);


  		




  290
  
  
    
	LD_6_n	<=	not Digits(6);


  		




  291
  
  
    
	LD_7_n	<=	not Digits(7);


  		




  292
  
  
    

  		




  293
  
  
    
	--	Time Multiplex


  		




  294
  
  
    
	process (CLK100MHz)


  		




  295
  
  
    
	begin


  		




  296
  
  
    
		if rising_edge(CLK100MHz) then


  		




  297
  
  
    
			if MuxCounter < MUXCOUNT-1 then


  		




  298
  
  
    
				MuxCounter <= MuxCounter + 1;


  		




  299
  
  
    
			else


  		




  300
  
  
    
				MuxCounter <= (others => '0');


  		




  301
  
  
    
				Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7);	--	Rotate Left


  		




  302
  
  
    
				Enable <= '0';


  		




  303
  
  
    
			end if;


  		




  304
  
  
    
			if MuxCounter > (MUXCOUNT-4) then


  		




  305
  
  
    
				Enable <= '1';


  		




  306
  
  
    
			end if;


  		




  307
  
  
    
		end if;


  		




  308
  
  
    
	end process;


  		




  309
  
  
    

  		




  310
  
  
    
	--	HEX to 7 Segmet Decoder


  		




  311
  
  
    
	--	 --     A


  		




  312
  
  
    
	--	|  |  F   B


  		




  313
  
  
    
	--	 --     G


  		




  314
  
  
    
	--	|  |  E   C


  		




  315
  
  
    
	--	 --     D   H


  		




  316
  
  
    
	--              ABCDEFGH


  		




  317
  
  
    
	Segments		<=	"11111100"	when	Code="0000"	else	--	Digit 0


  		




  318
  
  
    
						"01100000"	when	Code="0001"	else	--	Digit 1


  		




  319
  
  
    
						"11011010"	when	Code="0010"	else	--	Digit 2


  		




  320
  
  
    
						"11110010"	when	Code="0011"	else	--	Digit 3


  		




  321
  
  
    
						"01100110"	when	Code="0100"	else	--	Digit 4


  		




  322
  
  
    
						"10110110"	when	Code="0101"	else	--	Digit 5


  		




  323
  
  
    
						"10111110"	when	Code="0110"	else	--	Digit 6


  		




  324
  
  
    
						"11100000"	when	Code="0111"	else	--	Digit 7


  		




  325
  
  
    
						"11111110"	when	Code="1000"	else	--	Digit 8


  		




  326
  
  
    
						"11110110"	when	Code="1001"	else	--	Digit 9


  		




  327
  
  
    
						"11101110"	when	Code="1010"	else	--	Digit A


  		




  328
  
  
    
						"00111110"	when	Code="1011"	else	--	Digit b


  		




  329
  
  
    
						"10011100"	when	Code="1100"	else	--	Digit C


  		




  330
  
  
    
						"01111010"	when	Code="1101"	else	--	Digit d


  		




  331
  
  
    
						"10011110"	when	Code="1110"	else	--	Digit E


  		




  332
  
  
    
						"10001110"	when	Code="1111"	else	--	Digit F


  		




  333
  
  
    
						"00000000";


  		




  334
  
  
    

  		




  335
  
  
    
	Code 			<=	Number( 3 downto  0)	when	Digits="00000001"	else


  		




  336
  
  
    
						Number( 7 downto  4)	when	Digits="00000010"	else


  		




  337
  
  
    
						Number(11 downto  8)	when	Digits="00000100"	else


  		




  338
  
  
    
						Number(15 downto 12)	when	Digits="00001000"	else


  		




  339
  
  
    
						Number(19 downto 16)	when	Digits="00010000"	else


  		




  340
  
  
    
						Number(23 downto 20)	when	Digits="00100000"	else


  		




  341
  
  
    
						Number(27 downto 24)	when	Digits="01000000"	else


  		




  342
  
  
    
						Number(31 downto 28)	when	Digits="10000000"	else


  		




  343
  
  
    
						"0000";


  		




  344
  
  
    

  		




  345
  
  
    

  		




  346
  
  
    

  		




  347
  
  
    
	-- Diferencial In/Outs


  		




  348
  
  
    
	-- ========================


  		




  349
  
  
    
   DIFbuffer1 : IBUFGDS


  		




  350
  
  
    
   generic map (


  		




  351
  
  
    
      DIFF_TERM => FALSE, -- Differential Termination 


  		




  352
  
  
    
      IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, 


  		




  353
  
  
    
                               -- "0"-"16" 


  		




  354
  
  
    
      IOSTANDARD => "LVPECL_33")


  		




  355
  
  
    
   port map (


  		




  356
  
  
    
      I => SD1AP,  -- Diff_p buffer input (connect directly to top-level port)


  		




  357
  
  
    
      IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)


  		




  358
  
  
    
      O => EXT_CLOCK  -- Buffer output - Counter INPUT


  		




  359
  
  
    
   );


  		




  360
  
  
    

  		




  361
  
  
    
	OBUFDS_inst : OBUFDS


  		




  362
  
  
    
   generic map (


  		




  363
  
  
    
      IOSTANDARD => "LVDS_33")


  		




  364
  
  
    
   port map (


  		




  365
  
  
    
      O => SD2AP,     -- Diff_p output (connect directly to top-level port)


  		




  366
  
  
    
      OB => SD2AN,   -- Diff_n output (connect directly to top-level port)


  		




  367
  
  
    
      I => EXT_CLOCK      -- Buffer input are connected directly to IBUFGDS


  		




  368
  
  
    
   );


  		




  369
  
  
    
	


  		




  370
  
  
    
	--	Output Signal on SATA Connector


  		




  371
  
  
    
--	SD1AP			<=	'Z';	-- Counter INPUT


  		




  372
  
  
    
--	SD1AN			<=	'Z';


  		




  373
  
  
    
	SD1BP			<=	'Z';


  		




  374
  
  
    
	SD1BN			<=	'Z';


  		




  375
  
  
    

  		




  376
  
  
    
	--	Input Here via SATA Cable


  		




  377
  
  
    
--	SD2AP			<=	'Z';	-- Counter OUTPUT


  		




  378
  
  
    
--	SD2AN			<=	'Z';


  		




  379
  
  
    
	SD2BP			<=	'Z';


  		




  380
  
  
    
	SD2BN			<=	'Z';


  		




  381
  
  
    

  		




  382
  
  
    

  		




  383
  
  
    
	--	Unused Signals


  		




  384
  
  
    
	--	==============


  		




  385
  
  
    

  		




  386
  
  
    
	-- Differential inputs onn header


  		




  387
  
  
    
	DIF1N <= 'Z';


  		




  388
  
  
    
	DIF1P <= 'Z';


  		




  389
  
  
    
	DIF2N <= 'Z';


  		




  390
  
  
    
	DIF2P <= 'Z';


  		




  391
  
  
    

  		




  392
  
  
    
	--	I2C Signals (on connector J30)


  		




  393
  
  
    
	I2C_SCL		<=	'Z';


  		




  394
  
  
    
	I2C_SDA		<=	'Z';


  		




  395
  
  
    

  		




  396
  
  
    
	--	SPI Memory Interface


  		




  397
  
  
    
	SPI_CS_n		<=	'Z';


  		




  398
  
  
    
	SPI_DO		<=	'Z';


  		




  399
  
  
    
	SPI_DI		<=	'Z';


  		




  400
  
  
    
	SPI_CLK		<=	'Z';


  		




  401
  
  
    
	SPI_WP_n		<=	'Z';


  		




  402
  
  
    

  		




  403
  
  
    
	-- A/D


  		




  404
  
  
    
   ANA_OUTD	<= 'Z';


  		




  405
  
  
    
	ANA_REFD <= 'Z';


  		




  406
  
  
    

  		




  407
  
  
    
	-- VGA


  		




  408
  
  
    
	VGA_R	<= "ZZ";


  		




  409
  
  
    
	VGA_G	<= "ZZ";


  		




  410
  
  
    
	VGA_B	<= "ZZ";


  		




  411
  
  
    
	VGA_VS	<= 'Z';


  		




  412
  
  
    
	VGA_HS	<= 'Z';


  		




  413
  
  
    

  		




  414
  
  
    
	-- PS2


  		




  415
  
  
    
	PS2_DATA2 <= 'Z';


  		




  416
  
  
    
	PS2_CLK2 <='Z';


  		




  417
  
  
    

  		




  418
  
  
    
end architecture AtomicCounter_a;


  		












  

    
      Designs/Measuring_instruments/AtomicCounter/VHDL/atomiccounter.svf
    
  





  1
  
  
    
// Created using Xilinx Cse Software [ISE - 14.6]


  		




  2
  
  
    
// Date: Tue Jul 23 22:30:48 2013


  		




  3
  
  
    

  		




  4
  
  
    
TRST OFF;


  		




  5
  
  
    
ENDIR IDLE;


  		




  6
  
  
    
ENDDR IDLE;


  		




  7
  
  
    
STATE RESET;


  		




  8
  
  
    
STATE IDLE;


  		




  9
  
  
    
FREQUENCY 1E6 HZ;


  		




  10
  
  
    
//Operation: Program -p 0 -onlyFpga 


  		




  11
  
  
    
TIR 0 ;


  		




  12
  
  
    
HIR 0 ;


  		




  13
  
  
    
HDR 0 ;


  		




  14
  
  
    
TDR 0 ;


  		




  15
  
  
    
//Loading device with 'idcode' instruction.


  		




  16
  
  
    
SIR 6 TDI (09) SMASK (3f) ;


  		




  17
  
  
    
SDR 32 TDI (00000000) SMASK (ffffffff) TDO (f2610093) MASK (0fffffff) ;


  		




  18
  
  
    
TIR 0 ;


  		




  19
  
  
    
HIR 0 ;


  		




  20
  
  
    
TDR 0 ;


  		




  21
  
  
    
HDR 0 ;


  		




  22
  
  
    
TIR 0 ;


  		




  23
  
  
    
HIR 0 ;


  		




  24
  
  
    
HDR 0 ;


  		




  25
  
  
    
TDR 0 ;


  		




  26
  
  
    
//Loading device with 'idcode' instruction.


  		




  27
  
  
    
SIR 6 TDI (09) ;


  		




  28
  
  
    
SDR 32 TDI (00000000) TDO (f2610093) ;


  		




  29
  
  
    
//Boundary Scan Chain Contents


  		




  30
  
  
    
//Position 1: xc3s50an


  		




  31
  
  
    
TIR 0 ;


  		




  32
  
  
    
HIR 0 ;


  		




  33
  
  
    
TDR 0 ;


  		




  34
  
  
    
HDR 0 ;


  		




  35
  
  
    
TIR 0 ;


  		




  36
  
  
    
HIR 0 ;


  		




  37
  
  
    
TDR 0 ;


  		




  38
  
  
    
HDR 0 ;


  		




  39
  
  
    
TIR 0 ;


  		




  40
  
  
    
HIR 0 ;


  		




  41
  
  
    
HDR 0 ;


  		




  42
  
  
    
TDR 0 ;


  		




  43
  
  
    
//Loading device with 'idcode' instruction.


  		




  44
  
  
    
SIR 6 TDI (09) ;


  		




  45
  
  
    
SDR 32 TDI (00000000) TDO (f2610093) ;


  		




  46
  
  
    
//Loading device with 'bypass' instruction.


  		




  47
  
  
    
SIR 6 TDI (3f) ;


  		




  48
  
  
    
// Loading device with a `jprogram` instruction. 


  		




  49
  
  
    
SIR 6 TDI (0b) ;


  		




  50
  
  
    
// Loading device with a `cfg_in` instruction. 


  		




  51
  
  
    
SIR 6 TDI (05) ;


  		




  52
  
  
    
RUNTEST 10000 TCK;


  		




  53
  
  
    
// Loading device with a `cfg_in` instruction. 


  		




  54
  
  
    
SIR 6 TDI (05) ;


  		




  55
  
  
    
SDR 32 TDI (00000000) SMASK (ffffffff) ;


  		




  56
  
  
    
SIR 6 TDI (05) TDO (00) MASK (00) ;


  		




  57
  
  
    
SDR 437376 TDI (0004000400040004000400040004000400040004000400040004000400040004b000850c8a54d400400c8100830c8100870ca000850c0004000400040004c000850c5000850cc4707c00400c000000000000000000000000000000000000000000000000000000000000000000000000000000


  		




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  519
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  520
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  521
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  522
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  523
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  524
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  525
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  526
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  527
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  528
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  529
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  530
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  531
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  532
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  533
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  534
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  535
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  536
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  537
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  538
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  539
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  540
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  541
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  542
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  543
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  544
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  545
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  546
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  547
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		




  548
  
  
    
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff


  		








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