o: ActiveSupport::Cache::Entry :@compressedF: @value"2g",g
Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc
1 
*PADS-PCB*
2 
*PART*
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C1               C-ELYT,10uF@ELYTB
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C2               C,100nF@C0805
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C3               C,100nF@C0805
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C4               C,100nF@C0805
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D1               D,M4@MELF
8 
J1               SATA,JUMP7@SATA
9 
J12              JUMP2X3,JUMP2X3@JUMP2X3
10 
J13              JUMP2X2,JUMP2X2@JUMP2X2
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J2               SATA,JUMP7@SATA
12 
J3               SATA,JUMP7@SATA
13 
J4               SATA,JUMP7@SATA
14 
M1               PAD,HOLE_M3@HOLE_M3
15 
M2               PAD,HOLE_M3@HOLE_M3
16 
M3               PAD,HOLE_M3@HOLE_M3
17 
M4               PAD,HOLE_M3@HOLE_M3
18 
M5               FIDU_PASTE,FIDU_PASTE@FIDU_PASTE
19 
M6               FIDU,FIDU@FIDU
20 
R1               R,127@R0805
21 
R2               R,127@R0805
22 
R3               R,83@R0805
23 
R4               R,83@R0805
24 
U1               SO16_150,SY100S834L@SO16_150
25 

  		




  
  26
  
    
*NET*


  		




  
  27
  
    
*SIGNAL* GND


  		




  
  28
  
    
J2.1 J2.4 J2.7 M2.1 D1.A M3.1 M4.1 J12.1


  		




  
  29
  
    
J12.2 J12.5 J12.6 C2.1 C1.C M1.1 C3.1 J1.1


  		




  
  30
  
    
J1.4 J1.7 R3.1 R4.1 C4.1 J3.1 J3.4 J3.7


  		




  
  31
  
    
J4.1 J4.4 J4.7 U1.9


  		




  
  32
  
    
*SIGNAL* N27272


  		




  
  33
  
    
J1.2 R3.2 R1.1 U1.15


  		




  
  34
  
    
*SIGNAL* N27304


  		




  
  35
  
    
J1.5 R4.2 R2.1 U1.10


  		




  
  36
  
    
*SIGNAL* N28535


  		




  
  37
  
    
C4.2 J13.1 J13.2 U1.11


  		




  
  38
  
    
*SIGNAL* N28645


  		




  
  39
  
    
J13.3 J13.4 U1.14


  		




  
  40
  
    
*SIGNAL* N29135


  		




  
  41
  
    
J3.3 U1.2


  		




  
  42
  
    
*SIGNAL* N29489


  		




  
  43
  
    
J3.2 U1.1


  		




  
  44
  
    
*SIGNAL* N29759


  		




  
  45
  
    
J4.5 U1.4


  		




  
  46
  
    
*SIGNAL* N29767


  		




  
  47
  
    
J4.6 U1.5


  		




  
  48
  
    
*SIGNAL* N29775


  		




  
  49
  
    
J4.2 U1.7


  		




  
  50
  
    
*SIGNAL* N29783


  		




  
  51
  
    
J4.3 U1.8


  		




  
  52
  
    
*SIGNAL* N30203


  		




  
  53
  
    
J2.2 U1.13


  		




  
  54
  
    
*SIGNAL* N30210


  		




  
  55
  
    
J2.3 U1.12


  		




  
  56
  
    
*SIGNAL* VCC


  		




  
  57
  
    
D1.C J12.3 J12.4 C2.2 C1.A C3.2 R2.2 R1.2


  		




  
  58
  
    
U1.3 U1.6 U1.16


  		




  
  59
  
    
*END*


  		












  

    
      Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj
    
  





  
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(ExpressProject "CLKDIV"


  		




  
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  (Folder "Design Resources"


  		




  
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    (Folder "Library")


  		




  
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    (DRC_Check_Ports "FALSE")


  		




  
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    (DRC_Check_Off-Page_Connectors "FALSE")


  		




  
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    (DRC_Report_Ports_and_Off-page_Connectors "FALSE")


  		




  
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    (DRC_SDT_Compatibility "FALSE")


  		




  
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    (DRC_Report_Off-grid_Objects "FALSE")


  		




  
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    (DRC_Check_Unconnected_Nets "TRUE")


  		




  
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    (DRC_Check_for_Misleading_TAP "FALSE")


  		




  
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    (DRC_Report_Netnames "FALSE")


  		




  
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    (DRC_Check_Single_Node_Nets "TRUE")


  		




  
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    (DRC_Check_No_Driving_Source "TRUE")


  		




  
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    (DRC_Check_Floating_Pins "TRUE")


  		




  
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    (DRC_Check_Physical_Power_Pins_Visibility "TRUE")


  		




  
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    (DRC_Identical_References "TRUE")


  		




  
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    (DRC_Type_Mismatch "TRUE")


  		




  
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    (DRC_Report_Unused_Part_Packages "TRUE")


  		




  
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    (OTHER_PCB_Footprint "{Device},{Value}@{PCB Footprint}")


  		




  
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    (File ".\clkdiv.drc"


  		




  
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    (File ".\clkdiv.asc"


  		




  
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:@created_atf1424823413.07038594:@expires_in0