o: ActiveSupport::Cache::Entry :@compressedF: @value"·"±
gtime.xise
9 9
    <!-- along with the project source files, is sufficient to open and    -->
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    <!-- implement in ISE Project Navigator.                               -->
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    <!--                                                                   -->
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    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
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    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
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  </header>
14 14

  
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  <version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
15
  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
16 16

  
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  <files>
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    <file xil_pn:name="src/gtime.vhd" xil_pn:type="FILE_VHDL">
......
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    <property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
48 48
    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
49 49
    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
50
    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
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    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
51 51
    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
52 52
    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
53 53
    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
:@created_atf1419499146.151603łĘ:@expires_in0