     # Main Clock (Embedded 100MHz board oscillator)
     NET "CLK100MHz"	LOC = P60  |IOSTANDARD = LVCMOS33;
     #NET "CLK100MHz"	LOC = P125 | IOSTANDARD = LVCMOS33;
     #NET "SCLK"	LOC = P1  |IOSTANDARD = LVCMOS33;
     NET "CLK100MHz"	TNM_NET = CLK100MHz;
     TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%;
     NET "LO_CLOCK"	TNM_NET = LO_CLOCK;
     TIMESPEC TS_LO_CLOCK = PERIOD "LO_CLOCK" 4.5 ns HIGH 50%;
     NET "EXT_CLOCK"	TNM_NET = EXT_CLOCK;
     TIMESPEC TS_EXT_CLOCK = PERIOD "EXT_CLOCK" 4.5 ns HIGH 50%;
     #NET "SCLK"	TNM_NET = SCLK;
     #TIMESPEC TS_SCLK = PERIOD "SCLK" 50 MHz HIGH 10%;
     NET "B<0>" CLOCK_DEDICATED_ROUTE = FALSE;
     # For DCM connection across the whole chip
     NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE;
     NET "PS2_CLK2"  CLOCK_DEDICATED_ROUTE = FALSE;

     entity gtime is
     	generic (
     		--	Top Value for 100MHz Clock Counter
     --!!!KAKL		MAXCOUNT:	integer	:=	30_000_000;
     		MAXCOUNT:	integer	:=	10_000;
     		MAXCOUNT:	integer	:=	10_000;				-- Maximum for the first counter
     		MUXCOUNT:	integer	:=	100_000				--	LED Display Multiplex Clock Divider
     	);
     	port (
     		-- Main Clock
     		-- Clock on PCB
     		CLK100MHz:	in		std_logic;
     		-- Mode Signals (usualy not used)
     		M:				in		std_logic_vector(2 downto 0);
     		VS:			in		std_logic_vector(2 downto 0);
-...
     		B:				inout		std_logic_vector(24 downto 0);
     		-- PS/2 Bidirectional Port (open collector, J31 and J32)
     --		PS2_CLK1:	inout	std_logic;
     --		PS2_DATA1:	inout	std_logic;
     		PS2_CLK1:	inout	std_logic;
     		PS2_DATA1:	inout	std_logic;
     		PS2_CLK2:	inout	std_logic;
     		PS2_DATA2:	inout	std_logic;
-...
     architecture gtime_a of gtime is
     function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is
     variable i : integer:=0;
     variable mybcd : std_logic_vector(19 downto 0) := (others => '0');
     variable bint : std_logic_vector(15 downto 0) := bin;
     begin
     	for i in 0 to 15 loop  -- repeating 16 times.
     		mybcd(19 downto 1) := mybcd(18 downto 0);  --shifting the bits.
     		mybcd(0) := bint(15);
     		bint(15 downto 1) := bint(14 downto 0);
     		bint(0) :='0';
     		if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
     		mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
     		end if;
     		if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
     		mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
     		end if;
     		if(i < 15 and mybcd(11 downto 8) > "0100") then  --add 3 if BCD digit is greater than 4.
     		mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
     		end if;
     		if(i < 15 and mybcd(15 downto 12) > "0100") then  --add 3 if BCD digit is greater than 4.
     		mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);
     		end if;
     		if(i < 15 and mybcd(19 downto 16) > "0100") then  --add 3 if BCD digit is greater than 4.
     		mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);
     		end if;
     	end loop;
     	return mybcd;
     end to_bcd;
     	-- LED Demo Signals
     	-- Counter
     	--	----------------
     	signal Counter:			unsigned(13 downto 0)	:= "00000000000000";		--	Main Counter 1 Hz, max. 9.999 kHz (binary)
     	signal CounterMaxcount:	unsigned(14 downto 0)	:= "000000000000000";	--	Main Counter 10 kHz, max. 327.67 MHz (binary)
     	signal Bar:					unsigned(7 downto 0)		:=	X"00";					--	Register for Bar output (binary)
     	signal Counter:			unsigned(31 downto 0)	:= X"00000000";		--	Main Counter 2 Hz (binary)
     	--	LED Display
     	--	-----------
     	signal NumberPom:	std_logic_vector(35 downto 0) :=	X"000000000";				--	LED Display Input
     	signal Number:			std_logic_vector(35 downto 0) :=	X"000000000";				--	LED Display Input
     	signal Number:			std_logic_vector(31 downto 0) :=	X"00000000";				--	LED Display Input
     	signal Freq:			std_logic_vector(31 downto 0) :=	X"00000000";				--	Measured Frequency
     	signal HalfFreq:		std_logic_vector(31 downto 0);
     	signal MuxCounter:	unsigned(31 downto 0)	:=	(others => '0');	--	LED Multiplex - Multiplex Clock Divider
     	signal Enable:			std_logic;
     	signal Digits:			std_logic_vector(7 downto 0)	:=	X"01";	--	LED Multiplex - Digit Counter - LED Digit Output
-...
     	signal Code:			std_logic_vector(3 downto 0);					--	BCD to 7 Segment Decoder Output
     	signal LO_CLOCK:	std_logic;
     	signal EXT_CLOCK:	std_logic;
     --	signal LO_CLOCK:	std_logic;		-- Frequency divided by 2
     	signal EXT_CLOCK:	std_logic;		-- Input Frequency
     	signal Decko:	std_logic;
     	signal State:	unsigned(2 downto 0)	:=	(others => '0');
     	signal Decko:	std_logic;												-- D flip-flop
     	signal State:	unsigned(2 downto 0)	:=	(others => '0');		-- Inner states of automata
     	signal SCLK:	std_logic;
     	signal SCLK2:	std_logic;
     begin
     	-- Counter
     	process (EXT_CLOCK)
     	begin
     		if rising_edge(EXT_CLOCK) then
     			LO_CLOCK <= not LO_CLOCK;
     		end if;
     	end process;
     	-- Counter
     	process (LO_CLOCK)
     	begin
     		if rising_edge(LO_CLOCK) then
     			if (State = 3) or (State = 0) then
     				if Counter < MAXCOUNT-1 then
     					Counter <= Counter + 1;
     				else
     					Counter <= (others => '0');
     					CounterMaxcount <= CounterMaxcount + 1;
     				end if;
     			if (State = 2) or (State = 0) then
     				Counter <= Counter + 1;
     			end if;
     			if (State = 1) then
     				Freq(15  downto 0) <= std_logic_vector("00"&Counter);
     				Freq(31 downto 16) <= std_logic_vector("0"&CounterMaxcount);
     			end if;
     			if (State = 2) then
     				CounterMaxcount <= (others => '0');
     				Freq(31  downto 0) <= std_logic_vector(Counter);
     				Counter <= (others => '0');
     			end if;
     		end if;
-...
     	-- Sampling 1PPS signal
     	process (LO_CLOCK)
     	process (EXT_CLOCK)
     	begin
     		if rising_edge(LO_CLOCK) then
     		if rising_edge(EXT_CLOCK) then
     			Decko <= B(22);
     		end if;
     	end process;
     	-- Automata for controling the Counter
     	process (LO_CLOCK)
     	-- Automata for controlling the Counter
     	process (EXT_CLOCK)
     	begin
     		if rising_edge(LO_CLOCK) then
     		if rising_edge(EXT_CLOCK) then
     			if (Decko = '1') then
     				if (State < 3) then
     				if (State < 2) then
     					State <= State + 1;
     				end if;
     			else
-...
     	process (Decko)
        begin
     		if falling_edge(Decko) then
     			NumberPom(15  downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0);
     			NumberPom(35 downto 16) <=	to_bcd(Freq(31 downto 16))(19 downto 0);
     		if Decko = '0' then
     			LED(6) <= '1';
     		else
     			LED(6) <= '0';
     		end if;
     	end process;
     	Number(35 downto 0) <=	NumberPom(35 downto 0);
     	LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
     	LED(6 downto 4) <= (others => '0');
     	LED(3 downto 0) <= Number(35 downto 32); --	Disply 100-th of MHz on LEDbar
     	SCLK <= B(0);
     --	SCLK2 <= ((not Decko) OR SCLK);
     	process (Decko,SCLK)
        begin
     		if (Decko = '0') then
     			Number(31 downto 0) <= Freq(31 downto 0);
     		else
     			if rising_edge(SCLK) then
     				Number(30 downto 0) <= Number(31 downto 1);
     			end if;
     		end if;
     	end process;
     	B(1) <= Number(0);
     	B(2) <= Decko;
     	LED(7) <= Decko; -- Display 1PPS pulse on LEDbar
     	LED(5 downto 0) <= (others => '0');
     	--	LED Display (multiplexed)
     	--	=========================
-...
     						"0000";
     	-- Diferencial In/Outs
     	-- ========================
        DIFbuffer1 : IBUFGDS
        generic map (
           DIFF_TERM => FALSE, -- Differential Termination
           IBUF_DELAY_VALUE => "16", -- Specify the amount of added input delay for buffer,
           IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
                                    -- "0"-"16"
           IOSTANDARD => "DEFAULT")
           IOSTANDARD => "LVPECL_33")
        port map (
           I => SD1AP,  -- Diff_p buffer input (connect directly to top-level port)
           IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
           O => EXT_CLOCK  -- Buffer output
           O => EXT_CLOCK  -- Buffer output - Counter INPUT
        );
     	OBUFDS_inst : OBUFDS
        generic map (
           IOSTANDARD => "DEFAULT")
           IOSTANDARD => "LVDS_33")
        port map (
           O => SD2AP,     -- Diff_p output (connect directly to top-level port)
           OB => SD2AN,   -- Diff_n output (connect directly to top-level port)
           I => EXT_CLOCK      -- Buffer input
           I => EXT_CLOCK      -- Buffer input are connected directly to IBUFGDS
        );
     	--	Output Signal on SATA Connector
     --	SD1AP			<=	'Z';
     --	SD1AP			<=	'Z';	-- Counter INPUT
     --	SD1AN			<=	'Z';
     	SD1BP			<=	'Z';
     	SD1BN			<=	'Z';
     	--	Input Here via SATA Cable
     --	SD2AP			<=	'Z';
     --	SD2AP			<=	'Z';	-- Counter OUTPUT
     --	SD2AN			<=	'Z';
     	SD2BP			<=	'Z';
     	SD2BN			<=	'Z';
-...
     	--	Unused Signals
     	--	==============
     	-- Differential inputs onn header
     	DIF1N <= 'Z';
     	DIF1P <= 'Z';
     	DIF2N <= 'Z';
     	DIF2P <= 'Z';
     	--	I2C Signals (on connector J30)
     	I2C_SCL		<=	'Z';
     	I2C_SDA		<=	'Z';
-...
     	SPI_CLK		<=	'Z';
     	SPI_WP_n		<=	'Z';
     	-- A/D
        ANA_OUTD	<= 'Z';
     	ANA_REFD <= 'Z';
     	-- VGA
     	VGA_R	<= "ZZ";
     	VGA_G	<= "ZZ";
     	VGA_B	<= "ZZ";
     	VGA_VS	<= 'Z';
     	VGA_HS	<= 'Z';
     	-- PS2
     	PS2_DATA2 <= 'Z';
     	PS2_CLK2 <='Z';
     end architecture gtime_a;

         <!-- along with the project source files, is sufficient to open and    -->
         <!-- implement in ISE Project Navigator.                               -->
         <!--                                                                   -->
         <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
         <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
       </header>
       <version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
       <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
       <files>
         <file xil_pn:name="src/gtime.vhd" xil_pn:type="FILE_VHDL">
-...
         <property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
         <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
         <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
         <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
         <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
         <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
         <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
         <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>