| Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ILA.cdc | ||
|---|---|---|
| 1 |
#ChipScope Core Inserter Project File Version 3.0 |
|
| 2 |
#Tue May 07 14:15:34 CEST 2013 |
|
| 3 |
Project.device.designInputFile=D\:\\Documents\\xilinx\\PulseGenDiffInput\\PulseGen_cs.ngc |
|
| 4 |
Project.device.designOutputFile=D\:\\Documents\\xilinx\\PulseGenDiffInput\\PulseGen_cs.ngc |
|
| 5 |
Project.device.deviceFamily=15 |
|
| 6 |
Project.device.enableRPMs=true |
|
| 7 |
Project.device.outputDirectory=D\:\\Documents\\xilinx\\PulseGenDiffInput\\_ngo |
|
| 8 |
Project.device.useSRL16=true |
|
| 9 |
Project.filter.dimension=1 |
|
| 10 |
Project.filter<0>= |
|
| 11 |
Project.icon.boundaryScanChain=1 |
|
| 12 |
Project.icon.enableExtTriggerIn=false |
|
| 13 |
Project.icon.enableExtTriggerOut=false |
|
| 14 |
Project.icon.triggerInPinName= |
|
| 15 |
Project.icon.triggerOutPinName= |
|
| 16 |
Project.unit.dimension=1 |
|
| 17 |
Project.unit<0>.clockChannel=CLK100MHz_BUFGP |
|
| 18 |
Project.unit<0>.clockEdge=Rising |
|
| 19 |
Project.unit<0>.dataDepth=512 |
|
| 20 |
Project.unit<0>.dataEqualsTrigger=true |
|
| 21 |
Project.unit<0>.dataPortWidth=16 |
|
| 22 |
Project.unit<0>.enableGaps=false |
|
| 23 |
Project.unit<0>.enableStorageQualification=true |
|
| 24 |
Project.unit<0>.enableTimestamps=false |
|
| 25 |
Project.unit<0>.timestampDepth=0 |
|
| 26 |
Project.unit<0>.timestampWidth=0 |
|
| 27 |
Project.unit<0>.triggerChannel<0><0>=Counter<0> |
|
| 28 |
Project.unit<0>.triggerChannel<0><10>=Counter<18> |
|
| 29 |
Project.unit<0>.triggerChannel<0><11>=Counter<19> |
|
| 30 |
Project.unit<0>.triggerChannel<0><12>=Counter<2> |
|
| 31 |
Project.unit<0>.triggerChannel<0><13>=Counter<20> |
|
| 32 |
Project.unit<0>.triggerChannel<0><14>=Counter<21> |
|
| 33 |
Project.unit<0>.triggerChannel<0><15>=Counter<28> |
|
| 34 |
Project.unit<0>.triggerChannel<0><1>=Counter<1> |
|
| 35 |
Project.unit<0>.triggerChannel<0><2>=Counter<10> |
|
| 36 |
Project.unit<0>.triggerChannel<0><3>=Counter<11> |
|
| 37 |
Project.unit<0>.triggerChannel<0><4>=Counter<12> |
|
| 38 |
Project.unit<0>.triggerChannel<0><5>=Counter<13> |
|
| 39 |
Project.unit<0>.triggerChannel<0><6>=Counter<14> |
|
| 40 |
Project.unit<0>.triggerChannel<0><7>=Counter<15> |
|
| 41 |
Project.unit<0>.triggerChannel<0><8>=Counter<16> |
|
| 42 |
Project.unit<0>.triggerChannel<0><9>=Counter<17> |
|
| 43 |
Project.unit<0>.triggerConditionCountWidth=0 |
|
| 44 |
Project.unit<0>.triggerMatchCount<0>=2 |
|
| 45 |
Project.unit<0>.triggerMatchCountWidth<0><0>=4 |
|
| 46 |
Project.unit<0>.triggerMatchCountWidth<0><1>=4 |
|
| 47 |
Project.unit<0>.triggerMatchType<0><0>=1 |
|
| 48 |
Project.unit<0>.triggerMatchType<0><1>=1 |
|
| 49 |
Project.unit<0>.triggerPortCount=1 |
|
| 50 |
Project.unit<0>.triggerPortIsData<0>=true |
|
| 51 |
Project.unit<0>.triggerPortWidth<0>=16 |
|
| 52 |
Project.unit<0>.triggerSequencerLevels=16 |
|
| 53 |
Project.unit<0>.triggerSequencerType=1 |
|
| 54 |
Project.unit<0>.type=ilapro |
|
| Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/S3AN01B.ucf | ||
|---|---|---|
| 1 |
# Board: www.mlab.cz S3AN01A |
|
| 2 |
# Device: XC3S50AN-4C |
|
| 3 |
# Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes |
|
| 4 |
# Main Clock (Embedded 100MHz board oscillator) |
|
| 5 |
NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33; |
|
| 6 |
#NET "CLK100MHz" LOC = P125 | IOSTANDARD = LVCMOS33; |
|
| 7 |
#NET "SCLK" LOC = P1 |IOSTANDARD = LVCMOS33; |
|
| 8 |
|
|
| 9 |
NET "CLK100MHz" TNM_NET = CLK100MHz; |
|
| 10 |
TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%; |
|
| 11 |
|
|
| 12 |
NET "EXT_CLOCK" TNM_NET = EXT_CLOCK; |
|
| 13 |
TIMESPEC TS_EXT_CLOCK = PERIOD "EXT_CLOCK" 4.5 ns HIGH 50%; |
|
| 14 |
|
|
| 15 |
#NET "SCLK" TNM_NET = SCLK; |
|
| 16 |
#TIMESPEC TS_SCLK = PERIOD "SCLK" 50 MHz HIGH 10%; |
|
| 17 |
NET "B<0>" CLOCK_DEDICATED_ROUTE = FALSE; |
|
| 18 |
|
|
| 19 |
# For DCM connection across the whole chip |
|
| 20 |
NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE; |
|
| 21 |
NET "PS2_CLK2" CLOCK_DEDICATED_ROUTE = FALSE; |
|
| 22 |
|
|
| 23 |
# Mode signals |
|
| 24 |
NET "M[0]" LOC = P38 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 25 |
NET "M[1]" LOC = P37 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M1 and M2 for boot from external SPI Flash Memory |
|
| 26 |
NET "M[2]" LOC = P39 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M2 for boot from internal Flash memory |
|
| 27 |
# SPI Flash Vendor Mode Select (for external SPI boot Flash) |
|
| 28 |
NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 29 |
NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 30 |
NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 31 |
|
|
| 32 |
# DIP Switches (positive signals with pull-down) |
|
| 33 |
NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 34 |
NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 35 |
NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 36 |
NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 37 |
NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 38 |
NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 39 |
NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 40 |
NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 41 |
|
|
| 42 |
# Push Buttons (positive signals with pull-down) |
|
| 43 |
NET "PB[0]" LOC = P121 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 44 |
NET "PB[1]" LOC = P120 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 45 |
NET "PB[2]" LOC = P117 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 46 |
NET "PB[3]" LOC = P116 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 47 |
|
|
| 48 |
# LED String (positive output signals) |
|
| 49 |
NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33; |
|
| 50 |
NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33; |
|
| 51 |
NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33; |
|
| 52 |
NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33; |
|
| 53 |
NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33; |
|
| 54 |
NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33; |
|
| 55 |
NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33; |
|
| 56 |
NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33; |
|
| 57 |
|
|
| 58 |
# LED Display Output Signals (negative, multiplexed) |
|
| 59 |
NET "LD_A_n" LOC = P15 |IOSTANDARD = LVCMOS33; |
|
| 60 |
NET "LD_B_n" LOC = P30 |IOSTANDARD = LVCMOS33; |
|
| 61 |
NET "LD_C_n" LOC = P21 |IOSTANDARD = LVCMOS33; |
|
| 62 |
NET "LD_D_n" LOC = P19 |IOSTANDARD = LVCMOS33; |
|
| 63 |
NET "LD_E_n" LOC = P18 |IOSTANDARD = LVCMOS33; |
|
| 64 |
NET "LD_F_n" LOC = P16 |IOSTANDARD = LVCMOS33; |
|
| 65 |
NET "LD_G_n" LOC = P24 |IOSTANDARD = LVCMOS33; |
|
| 66 |
NET "LD_DP_n" LOC = P20 |IOSTANDARD = LVCMOS33; |
|
| 67 |
|
|
| 68 |
NET "LD_0_n" LOC = P25 |IOSTANDARD = LVCMOS33; |
|
| 69 |
NET "LD_1_n" LOC = P31 |IOSTANDARD = LVCMOS33; |
|
| 70 |
NET "LD_2_n" LOC = P32 |IOSTANDARD = LVCMOS33; |
|
| 71 |
NET "LD_3_n" LOC = P13 |IOSTANDARD = LVCMOS33; # !!! Connect U1.13 with U1.33 |
|
| 72 |
NET "LD_4_n" LOC = P27 |IOSTANDARD = LVCMOS33; |
|
| 73 |
NET "LD_5_n" LOC = P29 |IOSTANDARD = LVCMOS33; |
|
| 74 |
NET "LD_6_n" LOC = P28 |IOSTANDARD = LVCMOS33; |
|
| 75 |
NET "LD_7_n" LOC = P12 |IOSTANDARD = LVCMOS33; # !!! Connect U1.12 with U1.35 |
|
| 76 |
# VGA Analog Display Connection (outputs) |
|
| 77 |
NET "VGA_R[0]" LOC = P3 |IOSTANDARD = LVCMOS33; |
|
| 78 |
NET "VGA_R[1]" LOC = P4 |IOSTANDARD = LVCMOS33; |
|
| 79 |
NET "VGA_G[0]" LOC = P5 |IOSTANDARD = LVCMOS33; |
|
| 80 |
NET "VGA_G[1]" LOC = P6 |IOSTANDARD = LVCMOS33; |
|
| 81 |
NET "VGA_B[0]" LOC = P7 |IOSTANDARD = LVCMOS33; |
|
| 82 |
NET "VGA_B[1]" LOC = P8 |IOSTANDARD = LVCMOS33; |
|
| 83 |
NET "VGA_VS" LOC = P10 |IOSTANDARD = LVCMOS33; |
|
| 84 |
NET "VGA_HS" LOC = P11 |IOSTANDARD = LVCMOS33; |
|
| 85 |
|
|
| 86 |
# Bank 1 Port (input for tests, pull-up) |
|
| 87 |
NET "B[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 88 |
NET "B[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 89 |
NET "B[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 90 |
NET "B[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 91 |
NET "B[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 92 |
NET "B[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 93 |
NET "B[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 94 |
NET "B[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 95 |
NET "B[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 96 |
NET "B[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 97 |
NET "B[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 98 |
NET "B[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 99 |
NET "B[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 100 |
NET "B[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 101 |
NET "B[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 102 |
NET "B[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 103 |
NET "B[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 104 |
NET "B[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 105 |
NET "B[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 106 |
NET "B[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 107 |
NET "B[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 108 |
NET "B[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 109 |
NET "B[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 110 |
NET "B[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 111 |
NET "B[24]" LOC = P97 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Connected with B[23] on PCB |
|
| 112 |
# PS/2 Bidirectional Port (open collector, J31 and J32) |
|
| 113 |
#NET "PS2_CLK1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # S3AN01A PCB Design has bug so these pins |
|
| 114 |
#NET "PS2_DATA1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # will be assinged after PCB redesign |
|
| 115 |
NET "PS2_CLK2" LOC = P42 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 116 |
NET "PS2_DATA2" LOC = P58 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 117 |
|
|
| 118 |
# Diferencial Signals on 4 pin header (J7) |
|
| 119 |
NET "DIF1P" LOC = P110 |IOSTANDARD = LVCMOS33 ; |
|
| 120 |
NET "DIF1N" LOC = P111 |IOSTANDARD = LVCMOS33 ; |
|
| 121 |
NET "DIF2P" LOC = P112 |IOSTANDARD = LVCMOS33 ; |
|
| 122 |
NET "DIF2N" LOC = P113 |IOSTANDARD = LVCMOS33 ; |
|
| 123 |
|
|
| 124 |
# I2C Signals (on connector J30) |
|
| 125 |
NET "I2C_SCL" LOC = P115 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 126 |
NET "I2C_SDA" LOC = P114 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 127 |
|
|
| 128 |
# Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
|
| 129 |
NET "SD1AP" LOC = P54 |IOSTANDARD = LVPECL_33; |
|
| 130 |
NET "SD1AN" LOC = P55 |IOSTANDARD = LVPECL_33; |
|
| 131 |
NET "SD1BP" LOC = P59 |IOSTANDARD = LVCMOS33 ; |
|
| 132 |
NET "SD1BN" LOC = P57 |IOSTANDARD = LVCMOS33 ; |
|
| 133 |
NET "SD2AP" LOC = P124 |IOSTANDARD = LVDS_33 ; |
|
| 134 |
NET "SD2AN" LOC = P126 |IOSTANDARD = LVDS_33 ; |
|
| 135 |
NET "SD2BP" LOC = P131 |IOSTANDARD = LVCMOS33 ; |
|
| 136 |
NET "SD2BN" LOC = P129 |IOSTANDARD = LVCMOS33 ; |
|
| 137 |
|
|
| 138 |
# SPI Memory Interface |
|
| 139 |
NET "SPI_CS_n" LOC = P41 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 140 |
NET "SPI_DO" LOC = P71 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 141 |
NET "SPI_DI" LOC = P62 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 142 |
NET "SPI_CLK" LOC = P72 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 143 |
NET "SPI_WP_n" LOC = P70 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 144 |
|
|
| 145 |
# Analog In Out |
|
| 146 |
NET "ANA_OUTD" LOC = P67 |IOSTANDARD = LVCMOS33; |
|
| 147 |
NET "ANA_REFD" LOC = P68 |IOSTANDARD = LVCMOS33; |
|
| 148 |
NET "ANA_IND" LOC = P69 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 149 |
|
|
| 150 |
/* |
|
| 151 |
# Used Signals (test points) |
|
| 152 |
NET "TPS1" LOC = P53 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
|
| 153 |
NET "TPS2" LOC = P125 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
|
| 154 |
NET "TPS3" LOC = P127 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
|
| 155 |
NET "TPS4" LOC = P130 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
|
| 156 |
NET "TPS5" LOC = P141 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
|
| 157 |
NET "TPS6" LOC = P123 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
|
| 158 |
NET "XXX1" LOC = P33 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only |
|
| 159 |
NET "XXX2" LOC = P35 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only |
|
| 160 |
*/ |
|
| Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/gtime.vhd | ||
|---|---|---|
| 1 |
---------------------------------------------------------------------------------- |
|
| 2 |
-- Company: www.mlab.cz |
|
| 3 |
-- Based on code written by MIHO. |
|
| 4 |
-- |
|
| 5 |
-- HW Design Name: S3AN01A |
|
| 6 |
-- Project Name: gtime |
|
| 7 |
-- Target Devices: XC3S50AN-4 |
|
| 8 |
-- Tool versions: ISE 13.3 |
|
| 9 |
-- Description: Time and frequency synchronisation for RDMS01A. |
|
| 10 |
-- |
|
| 11 |
-- Dependencies: CLKGEN01B, GPS01A, STM32F10xRxT01A |
|
| 12 |
-- |
|
| 13 |
-- Version: $Id$ |
|
| 14 |
-- |
|
| 15 |
---------------------------------------------------------------------------------- |
|
| 16 |
|
|
| 17 |
library IEEE; |
|
| 18 |
use IEEE.STD_LOGIC_1164.ALL; |
|
| 19 |
use IEEE.numeric_std.ALL; |
|
| 20 |
|
|
| 21 |
library UNISIM; |
|
| 22 |
use UNISIM.vcomponents.all; |
|
| 23 |
|
|
| 24 |
entity gtime is |
|
| 25 |
generic ( |
|
| 26 |
-- Top Value for 100MHz Clock Counter |
|
| 27 |
MAXCOUNT: integer := 10_000; -- Maximum for the first counter |
|
| 28 |
MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
|
| 29 |
); |
|
| 30 |
port ( |
|
| 31 |
-- Clock on PCB |
|
| 32 |
CLK100MHz: in std_logic; |
|
| 33 |
|
|
| 34 |
-- Mode Signals (usualy not used) |
|
| 35 |
M: in std_logic_vector(2 downto 0); |
|
| 36 |
VS: in std_logic_vector(2 downto 0); |
|
| 37 |
|
|
| 38 |
-- Dipswitch Inputs |
|
| 39 |
DIPSW: in std_logic_vector(7 downto 0); |
|
| 40 |
|
|
| 41 |
-- Push Buttons |
|
| 42 |
PB: in std_logic_vector(3 downto 0); |
|
| 43 |
|
|
| 44 |
-- LED Bar Outputs |
|
| 45 |
LED: out std_logic_vector(7 downto 0); |
|
| 46 |
|
|
| 47 |
-- LED Display (8 digit with 7 segments and ddecimal point) |
|
| 48 |
LD_A_n: out std_logic; |
|
| 49 |
LD_B_n: out std_logic; |
|
| 50 |
LD_C_n: out std_logic; |
|
| 51 |
LD_D_n: out std_logic; |
|
| 52 |
LD_E_n: out std_logic; |
|
| 53 |
LD_F_n: out std_logic; |
|
| 54 |
LD_G_n: out std_logic; |
|
| 55 |
LD_DP_n: out std_logic; |
|
| 56 |
LD_0_n: out std_logic; |
|
| 57 |
LD_1_n: out std_logic; |
|
| 58 |
LD_2_n: out std_logic; |
|
| 59 |
LD_3_n: out std_logic; |
|
| 60 |
LD_4_n: out std_logic; |
|
| 61 |
LD_5_n: out std_logic; |
|
| 62 |
LD_6_n: out std_logic; |
|
| 63 |
LD_7_n: out std_logic; |
|
| 64 |
|
|
| 65 |
-- VGA Video Out Port |
|
| 66 |
VGA_R: out std_logic_vector(1 downto 0); |
|
| 67 |
VGA_G: out std_logic_vector(1 downto 0); |
|
| 68 |
VGA_B: out std_logic_vector(1 downto 0); |
|
| 69 |
VGA_VS: out std_logic; |
|
| 70 |
VGA_HS: out std_logic; |
|
| 71 |
|
|
| 72 |
-- Bank 1 Pins - Inputs for this Test |
|
| 73 |
B: inout std_logic_vector(24 downto 0); |
|
| 74 |
|
|
| 75 |
-- PS/2 Bidirectional Port (open collector, J31 and J32) |
|
| 76 |
PS2_CLK1: inout std_logic; |
|
| 77 |
PS2_DATA1: inout std_logic; |
|
| 78 |
PS2_CLK2: inout std_logic; |
|
| 79 |
PS2_DATA2: inout std_logic; |
|
| 80 |
|
|
| 81 |
-- Diferencial Signals on 4 pin header (J7) |
|
| 82 |
DIF1P: inout std_logic; |
|
| 83 |
DIF1N: inout std_logic; |
|
| 84 |
DIF2P: inout std_logic; |
|
| 85 |
DIF2N: inout std_logic; |
|
| 86 |
|
|
| 87 |
|
|
| 88 |
-- I2C Signals (on connector J30) |
|
| 89 |
I2C_SCL: inout std_logic; |
|
| 90 |
I2C_SDA: inout std_logic; |
|
| 91 |
|
|
| 92 |
-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
|
| 93 |
SD1AP: inout std_logic; |
|
| 94 |
SD1AN: inout std_logic; |
|
| 95 |
SD1BP: inout std_logic; |
|
| 96 |
SD1BN: inout std_logic; |
|
| 97 |
SD2AP: inout std_logic; |
|
| 98 |
SD2AN: inout std_logic; |
|
| 99 |
SD2BP: inout std_logic; |
|
| 100 |
SD2BN: inout std_logic; |
|
| 101 |
|
|
| 102 |
-- Analog In Out |
|
| 103 |
ANA_OUTD: out std_logic; |
|
| 104 |
ANA_REFD: out std_logic; |
|
| 105 |
ANA_IND: in std_logic; |
|
| 106 |
|
|
| 107 |
-- SPI Memory Interface |
|
| 108 |
SPI_CS_n: inout std_logic; |
|
| 109 |
SPI_DO: inout std_logic; |
|
| 110 |
SPI_DI: inout std_logic; |
|
| 111 |
SPI_CLK: inout std_logic; |
|
| 112 |
SPI_WP_n: inout std_logic |
|
| 113 |
); |
|
| 114 |
end entity gtime; |
|
| 115 |
|
|
| 116 |
|
|
| 117 |
architecture gtime_a of gtime is |
|
| 118 |
|
|
| 119 |
|
|
| 120 |
-- Counter |
|
| 121 |
-- ---------------- |
|
| 122 |
|
|
| 123 |
signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter 2 Hz (binary) |
|
| 124 |
|
|
| 125 |
|
|
| 126 |
-- LED Display |
|
| 127 |
-- ----------- |
|
| 128 |
|
|
| 129 |
signal Number: std_logic_vector(31 downto 0) := X"00000000"; -- LED Display Input |
|
| 130 |
signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency |
|
| 131 |
signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
|
| 132 |
signal Enable: std_logic; |
|
| 133 |
signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
|
| 134 |
signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
|
| 135 |
signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
|
| 136 |
|
|
| 137 |
|
|
| 138 |
-- signal LO_CLOCK: std_logic; -- Frequency divided by 2 |
|
| 139 |
signal EXT_CLOCK: std_logic; -- Input Frequency |
|
| 140 |
|
|
| 141 |
signal Decko: std_logic; -- D flip-flop |
|
| 142 |
signal State: unsigned(2 downto 0) := (others => '0'); -- Inner states of automata |
|
| 143 |
|
|
| 144 |
signal SCLK: std_logic; |
|
| 145 |
signal SCLK2: std_logic; |
|
| 146 |
|
|
| 147 |
|
|
| 148 |
begin |
|
| 149 |
|
|
| 150 |
-- Counter |
|
| 151 |
process (EXT_CLOCK) |
|
| 152 |
begin |
|
| 153 |
|
|
| 154 |
if rising_edge(EXT_CLOCK) then |
|
| 155 |
|
|
| 156 |
if (State = 2) or (State = 0) then |
|
| 157 |
Counter <= Counter + 1; |
|
| 158 |
end if; |
|
| 159 |
if (State = 1) then |
|
| 160 |
Freq(31 downto 0) <= std_logic_vector(Counter); |
|
| 161 |
Counter <= (others => '0'); |
|
| 162 |
end if; |
|
| 163 |
end if; |
|
| 164 |
|
|
| 165 |
end process; |
|
| 166 |
|
|
| 167 |
|
|
| 168 |
-- Sampling 1PPS signal |
|
| 169 |
process (EXT_CLOCK) |
|
| 170 |
begin |
|
| 171 |
if rising_edge(EXT_CLOCK) then |
|
| 172 |
Decko <= B(22); |
|
| 173 |
end if; |
|
| 174 |
end process; |
|
| 175 |
|
|
| 176 |
-- Automata for controlling the Counter |
|
| 177 |
process (EXT_CLOCK) |
|
| 178 |
begin |
|
| 179 |
if rising_edge(EXT_CLOCK) then |
|
| 180 |
if (Decko = '1') then |
|
| 181 |
if (State < 2) then |
|
| 182 |
State <= State + 1; |
|
| 183 |
end if; |
|
| 184 |
else |
|
| 185 |
State <= (others => '0'); |
|
| 186 |
end if; |
|
| 187 |
end if; |
|
| 188 |
end process; |
|
| 189 |
|
|
| 190 |
process (Decko) |
|
| 191 |
begin |
|
| 192 |
if Decko = '0' then |
|
| 193 |
LED(6) <= '1'; |
|
| 194 |
else |
|
| 195 |
LED(6) <= '0'; |
|
| 196 |
end if; |
|
| 197 |
end process; |
|
| 198 |
|
|
| 199 |
SCLK <= B(0); |
|
| 200 |
|
|
| 201 |
-- Output Shift Register |
|
| 202 |
process (Decko,SCLK) |
|
| 203 |
begin |
|
| 204 |
if (Decko = '0') then |
|
| 205 |
Number(31 downto 0) <= Freq(31 downto 0); |
|
| 206 |
else |
|
| 207 |
if rising_edge(SCLK) then |
|
| 208 |
Number(30 downto 0) <= Number(31 downto 1); |
|
| 209 |
end if; |
|
| 210 |
end if; |
|
| 211 |
end process; |
|
| 212 |
|
|
| 213 |
B(1) <= Number(0); |
|
| 214 |
B(2) <= Decko; |
|
| 215 |
|
|
| 216 |
LED(7) <= Decko; -- Display 1PPS pulse on LEDbar |
|
| 217 |
LED(5 downto 0) <= (others => '0'); |
|
| 218 |
|
|
| 219 |
-- LED Display (multiplexed) |
|
| 220 |
-- ========================= |
|
| 221 |
|
|
| 222 |
-- Connect LED Display Output Ports (negative outputs) |
|
| 223 |
LD_A_n <= not (Segments(0) and Enable); |
|
| 224 |
LD_B_n <= not (Segments(1) and Enable); |
|
| 225 |
LD_C_n <= not (Segments(2) and Enable); |
|
| 226 |
LD_D_n <= not (Segments(3) and Enable); |
|
| 227 |
LD_E_n <= not (Segments(4) and Enable); |
|
| 228 |
LD_F_n <= not (Segments(5) and Enable); |
|
| 229 |
LD_G_n <= not (Segments(6) and Enable); |
|
| 230 |
LD_DP_n <= not (Segments(7) and Enable); |
|
| 231 |
|
|
| 232 |
LD_0_n <= not Digits(0); |
|
| 233 |
LD_1_n <= not Digits(1); |
|
| 234 |
LD_2_n <= not Digits(2); |
|
| 235 |
LD_3_n <= not Digits(3); |
|
| 236 |
LD_4_n <= not Digits(4); |
|
| 237 |
LD_5_n <= not Digits(5); |
|
| 238 |
LD_6_n <= not Digits(6); |
|
| 239 |
LD_7_n <= not Digits(7); |
|
| 240 |
|
|
| 241 |
-- Time Multiplex |
|
| 242 |
process (CLK100MHz) |
|
| 243 |
begin |
|
| 244 |
if rising_edge(CLK100MHz) then |
|
| 245 |
if MuxCounter < MUXCOUNT-1 then |
|
| 246 |
MuxCounter <= MuxCounter + 1; |
|
| 247 |
else |
|
| 248 |
MuxCounter <= (others => '0'); |
|
| 249 |
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left |
|
| 250 |
Enable <= '0'; |
|
| 251 |
end if; |
|
| 252 |
if MuxCounter > (MUXCOUNT-4) then |
|
| 253 |
Enable <= '1'; |
|
| 254 |
end if; |
|
| 255 |
end if; |
|
| 256 |
end process; |
|
| 257 |
|
|
| 258 |
-- HEX to 7 Segmet Decoder |
|
| 259 |
-- -- A |
|
| 260 |
-- | | F B |
|
| 261 |
-- -- G |
|
| 262 |
-- | | E C |
|
| 263 |
-- -- D H |
|
| 264 |
-- ABCDEFGH |
|
| 265 |
Segments <= "11111100" when Code="0000" else -- Digit 0 |
|
| 266 |
"01100000" when Code="0001" else -- Digit 1 |
|
| 267 |
"11011010" when Code="0010" else -- Digit 2 |
|
| 268 |
"11110010" when Code="0011" else -- Digit 3 |
|
| 269 |
"01100110" when Code="0100" else -- Digit 4 |
|
| 270 |
"10110110" when Code="0101" else -- Digit 5 |
|
| 271 |
"10111110" when Code="0110" else -- Digit 6 |
|
| 272 |
"11100000" when Code="0111" else -- Digit 7 |
|
| 273 |
"11111110" when Code="1000" else -- Digit 8 |
|
| 274 |
"11110110" when Code="1001" else -- Digit 9 |
|
| 275 |
"11101110" when Code="1010" else -- Digit A |
|
| 276 |
"00111110" when Code="1011" else -- Digit b |
|
| 277 |
"10011100" when Code="1100" else -- Digit C |
|
| 278 |
"01111010" when Code="1101" else -- Digit d |
|
| 279 |
"10011110" when Code="1110" else -- Digit E |
|
| 280 |
"10001110" when Code="1111" else -- Digit F |
|
| 281 |
"00000000"; |
|
| 282 |
|
|
| 283 |
Code <= Number( 3 downto 0) when Digits="00000001" else |
|
| 284 |
Number( 7 downto 4) when Digits="00000010" else |
|
| 285 |
Number(11 downto 8) when Digits="00000100" else |
|
| 286 |
Number(15 downto 12) when Digits="00001000" else |
|
| 287 |
Number(19 downto 16) when Digits="00010000" else |
|
| 288 |
Number(23 downto 20) when Digits="00100000" else |
|
| 289 |
Number(27 downto 24) when Digits="01000000" else |
|
| 290 |
Number(31 downto 28) when Digits="10000000" else |
|
| 291 |
"0000"; |
|
| 292 |
|
|
| 293 |
|
|
| 294 |
-- Diferencial In/Outs |
|
| 295 |
-- ======================== |
|
| 296 |
DIFbuffer1 : IBUFGDS |
|
| 297 |
generic map ( |
|
| 298 |
DIFF_TERM => FALSE, -- Differential Termination |
|
| 299 |
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, |
|
| 300 |
-- "0"-"16" |
|
| 301 |
IOSTANDARD => "LVPECL_33") |
|
| 302 |
port map ( |
|
| 303 |
I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |
|
| 304 |
IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) |
|
| 305 |
O => EXT_CLOCK -- Buffer output - Counter INPUT |
|
| 306 |
); |
|
| 307 |
|
|
| 308 |
OBUFDS_inst : OBUFDS |
|
| 309 |
generic map ( |
|
| 310 |
IOSTANDARD => "LVDS_33") |
|
| 311 |
port map ( |
|
| 312 |
O => SD2AP, -- Diff_p output (connect directly to top-level port) |
|
| 313 |
OB => SD2AN, -- Diff_n output (connect directly to top-level port) |
|
| 314 |
I => EXT_CLOCK -- Buffer input are connected directly to IBUFGDS |
|
| 315 |
); |
|
| 316 |
|
|
| 317 |
-- Output Signal on SATA Connector |
|
| 318 |
-- SD1AP <= 'Z'; -- Counter INPUT |
|
| 319 |
-- SD1AN <= 'Z'; |
|
| 320 |
SD1BP <= 'Z'; |
|
| 321 |
SD1BN <= 'Z'; |
|
| 322 |
|
|
| 323 |
-- Input Here via SATA Cable |
|
| 324 |
-- SD2AP <= 'Z'; -- Counter OUTPUT |
|
| 325 |
-- SD2AN <= 'Z'; |
|
| 326 |
SD2BP <= 'Z'; |
|
| 327 |
SD2BN <= 'Z'; |
|
| 328 |
|
|
| 329 |
|
|
| 330 |
-- Unused Signals |
|
| 331 |
-- ============== |
|
| 332 |
|
|
| 333 |
-- Differential inputs onn header |
|
| 334 |
DIF1N <= 'Z'; |
|
| 335 |
DIF1P <= 'Z'; |
|
| 336 |
DIF2N <= 'Z'; |
|
| 337 |
DIF2P <= 'Z'; |
|
| 338 |
|
|
| 339 |
-- I2C Signals (on connector J30) |
|
| 340 |
I2C_SCL <= 'Z'; |
|
| 341 |
I2C_SDA <= 'Z'; |
|
| 342 |
|
|
| 343 |
-- SPI Memory Interface |
|
| 344 |
SPI_CS_n <= 'Z'; |
|
| 345 |
SPI_DO <= 'Z'; |
|
| 346 |
SPI_DI <= 'Z'; |
|
| 347 |
SPI_CLK <= 'Z'; |
|
| 348 |
SPI_WP_n <= 'Z'; |
|
| 349 |
|
|
| 350 |
-- A/D |
|
| 351 |
ANA_OUTD <= 'Z'; |
|
| 352 |
ANA_REFD <= 'Z'; |
|
| 353 |
|
|
| 354 |
-- VGA |
|
| 355 |
VGA_R <= "ZZ"; |
|
| 356 |
VGA_G <= "ZZ"; |
|
| 357 |
VGA_B <= "ZZ"; |
|
| 358 |
VGA_VS <= 'Z'; |
|
| 359 |
VGA_HS <= 'Z'; |
|
| 360 |
|
|
| 361 |
-- PS2 |
|
| 362 |
PS2_DATA2 <= 'Z'; |
|
| 363 |
PS2_CLK2 <='Z'; |
|
| 364 |
|
|
| 365 |
end architecture gtime_a; |
|
| Designs/Measuring_instruments/RMDS01A/VHDL/gtime/gtime.xise | ||
|---|---|---|
| 1 |
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
|
| 2 |
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
|
| 3 |
|
|
| 4 |
<header> |
|
| 5 |
<!-- ISE source project file created by Project Navigator. --> |
|
| 6 |
<!-- --> |
|
| 7 |
<!-- This file contains project source information including a list of --> |
|
| 8 |
<!-- project source files, project and process properties. This file, --> |
|
| 9 |
<!-- along with the project source files, is sufficient to open and --> |
|
| 10 |
<!-- implement in ISE Project Navigator. --> |
|
| 11 |
<!-- --> |
|
| 12 |
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> |
|
| 13 |
</header> |
|
| 14 |
|
|
| 15 |
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/> |
|
| 16 |
|
|
| 17 |
<files> |
|
| 18 |
<file xil_pn:name="src/gtime.vhd" xil_pn:type="FILE_VHDL"> |
|
| 19 |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
|
| 20 |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
|
| 21 |
</file> |
|
| 22 |
<file xil_pn:name="src/S3AN01B.ucf" xil_pn:type="FILE_UCF"> |
|
| 23 |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
|
| 24 |
</file> |
|
| 25 |
</files> |
|
| 26 |
|
|
| 27 |
<properties> |
|
| 28 |
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 29 |
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 30 |
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 31 |
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 32 |
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 33 |
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 34 |
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 35 |
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 36 |
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 37 |
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 38 |
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 39 |
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 40 |
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
|
| 41 |
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 42 |
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 43 |
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> |
|
| 44 |
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/> |
|
| 45 |
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
|
| 46 |
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
|
| 47 |
<property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/> |
|
| 48 |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/> |
|
| 49 |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 50 |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 51 |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 52 |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 53 |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 54 |
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 55 |
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
|
| 56 |
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
|
| 57 |
<property xil_pn:name="Configuration Rate" xil_pn:value="25" xil_pn:valueState="default"/> |
|
| 58 |
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 59 |
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 60 |
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 61 |
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 62 |
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 63 |
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 64 |
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 65 |
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 66 |
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 67 |
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 68 |
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 69 |
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
|
| 70 |
<property xil_pn:name="Device" xil_pn:value="xc3s50an" xil_pn:valueState="non-default"/> |
|
| 71 |
<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/> |
|
| 72 |
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/> |
|
| 73 |
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 74 |
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
|
| 75 |
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 76 |
<property xil_pn:name="Drive Done Pin High" xil_pn:value="true" xil_pn:valueState="non-default"/> |
|
| 77 |
<property xil_pn:name="Dummy Driver for Enable Filter on Suspend Input" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 78 |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 79 |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 80 |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 81 |
<property xil_pn:name="Enable Filter on Suspend Input" xil_pn:value="Please use the ENABLE_SUSPEND implementation constraint." xil_pn:valueState="default"/> |
|
| 82 |
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 83 |
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 84 |
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 85 |
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> |
|
| 86 |
<property xil_pn:name="Enable Power-On Reset Detection" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 87 |
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 88 |
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 89 |
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> |
|
| 90 |
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 91 |
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 92 |
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/> |
|
| 93 |
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> |
|
| 94 |
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
|
| 95 |
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> |
|
| 96 |
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> |
|
| 97 |
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 98 |
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 99 |
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
|
| 100 |
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
|
| 101 |
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
|
| 102 |
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence" xil_pn:value="4" xil_pn:valueState="default"/> |
|
| 103 |
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence" xil_pn:value="5" xil_pn:valueState="default"/> |
|
| 104 |
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 105 |
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 106 |
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 107 |
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 108 |
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 109 |
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 110 |
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 111 |
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 112 |
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 113 |
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 114 |
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 115 |
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
|
| 116 |
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 117 |
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 118 |
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 119 |
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 120 |
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 121 |
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
|
| 122 |
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
|
| 123 |
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
|
| 124 |
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
|
| 125 |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
|
| 126 |
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 127 |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 128 |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|gtime|gtime_a" xil_pn:valueState="non-default"/> |
|
| 129 |
<property xil_pn:name="Implementation Top File" xil_pn:value="src/gtime.vhd" xil_pn:valueState="non-default"/> |
|
| 130 |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gtime" xil_pn:valueState="non-default"/> |
|
| 131 |
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 132 |
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 133 |
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 134 |
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 135 |
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 136 |
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 137 |
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
|
| 138 |
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
|
| 139 |
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
|
| 140 |
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
|
| 141 |
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
|
| 142 |
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
|
| 143 |
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
|
| 144 |
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
|
| 145 |
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
|
| 146 |
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 147 |
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 148 |
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 149 |
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 150 |
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 151 |
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 152 |
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/> |
|
| 153 |
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 154 |
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/> |
|
| 155 |
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
|
| 156 |
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
|
| 157 |
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 158 |
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 159 |
<property xil_pn:name="MultiBoot: Next Configuration Mode" xil_pn:value="001" xil_pn:valueState="default"/> |
|
| 160 |
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
|
| 161 |
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 162 |
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
|
| 163 |
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
|
| 164 |
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
|
| 165 |
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> |
|
| 166 |
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> |
|
| 167 |
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/> |
|
| 168 |
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> |
|
| 169 |
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
|
| 170 |
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> |
|
| 171 |
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
|
| 172 |
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/> |
|
| 173 |
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 174 |
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 175 |
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 176 |
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 177 |
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 178 |
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 179 |
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 180 |
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 181 |
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 182 |
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 183 |
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 184 |
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 185 |
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 186 |
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 187 |
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 188 |
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 189 |
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 190 |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 191 |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 192 |
<property xil_pn:name="Output File Name" xil_pn:value="gtime" xil_pn:valueState="default"/> |
|
| 193 |
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 194 |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
|
| 195 |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
|
| 196 |
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/> |
|
| 197 |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 198 |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 199 |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 200 |
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
|
| 201 |
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
|
| 202 |
<property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 203 |
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
|
| 204 |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
|
| 205 |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="gtime_map.vhd" xil_pn:valueState="default"/> |
|
| 206 |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="gtime_timesim.vhd" xil_pn:valueState="default"/> |
|
| 207 |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="gtime_synthesis.vhd" xil_pn:valueState="default"/> |
|
| 208 |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="gtime_translate.vhd" xil_pn:valueState="default"/> |
|
| 209 |
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 210 |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 211 |
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> |
|
| 212 |
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
|
| 213 |
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 214 |
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 215 |
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/> |
|
| 216 |
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
|
| 217 |
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 218 |
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
|
| 219 |
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 220 |
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
|
| 221 |
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 222 |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
|
| 223 |
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
|
| 224 |
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/> |
|
| 225 |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 226 |
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
|
| 227 |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
|
| 228 |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
|
| 229 |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="gtime" xil_pn:valueState="default"/> |
|
| 230 |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 231 |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 232 |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 233 |
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
|
| 234 |
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
|
| 235 |
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
|
| 236 |
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
|
| 237 |
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 238 |
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 239 |
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
|
| 240 |
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 241 |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 242 |
<property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 243 |
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
|
| 244 |
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 245 |
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 246 |
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 247 |
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 248 |
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 249 |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
|
| 250 |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
|
| 251 |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 252 |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 253 |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 254 |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 255 |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
|
| 256 |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 257 |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 258 |
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
|
| 259 |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
|
| 260 |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
|
| 261 |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
|
| 262 |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
|
| 263 |
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
|
| 264 |
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 265 |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
|
| 266 |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 267 |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> |
|
| 268 |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
|
| 269 |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
|
| 270 |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
|
| 271 |
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/> |
|
| 272 |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/> |
|
| 273 |
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> |
|
| 274 |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
|
| 275 |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
|
| 276 |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/> |
|
| 277 |
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
|
| 278 |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 279 |
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
|
| 280 |
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 281 |
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
|
| 282 |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
|
| 283 |
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 284 |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/> |
|
| 285 |
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 286 |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 287 |
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 288 |
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 289 |
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 290 |
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 291 |
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 292 |
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 293 |
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 294 |
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 295 |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 296 |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 297 |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 298 |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
|
| 299 |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 300 |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/> |
|
| 301 |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/> |
|
| 302 |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 303 |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/13.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/> |
|
| 304 |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
|
| 305 |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/> |
|
| 306 |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 307 |
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 308 |
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 309 |
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
|
| 310 |
<property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> |
|
| 311 |
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
|
| 312 |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
|
| 313 |
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/> |
|
| 314 |
<!-- --> |
|
| 315 |
<!-- The following properties are for internal use only. These should not be modified.--> |
|
| 316 |
<!-- --> |
|
| 317 |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 318 |
<property xil_pn:name="PROP_DesignName" xil_pn:value="gtime" xil_pn:valueState="non-default"/> |
|
| 319 |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/> |
|
| 320 |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
|
| 321 |
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 322 |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 323 |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 324 |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 325 |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
|
| 326 |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
|
| 327 |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-08-28T23:51:54" xil_pn:valueState="non-default"/> |
|
| 328 |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AAC6D7E01D414DD992A4DDE7C0B857EB" xil_pn:valueState="non-default"/> |
|
| 329 |
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
|
| 330 |
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
|
| 331 |
</properties> |
|
| 332 |
|
|
| 333 |
<bindings/> |
|
| 334 |
|
|
| 335 |
<libraries/> |
|
| 336 |
|
|
| 337 |
<autoManagedFiles> |
|
| 338 |
<!-- The following files are identified by `include statements in verilog --> |
|
| 339 |
<!-- source files and are automatically managed by Project Navigator. --> |
|
| 340 |
<!-- --> |
|
| 341 |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
|
| 342 |
<!-- project is analyzed based on files automatically identified as --> |
|
| 343 |
<!-- include files. --> |
|
| 344 |
</autoManagedFiles> |
|
| 345 |
|
|
| 346 |
</project> |
|
| Designs/Measuring_instruments/RMDS01A/HDL/gtime/src/S3AN01B.ucf | ||
|---|---|---|
| 1 |
# Board: www.mlab.cz S3AN01A |
|
| 2 |
# Device: XC3S50AN-4C |
|
| 3 |
# Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes |
|
| 4 |
# Main Clock (Embedded 100MHz board oscillator) |
|
| 5 |
NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33; |
|
| 6 |
#NET "CLK100MHz" LOC = P125 | IOSTANDARD = LVCMOS33; |
|
| 7 |
#NET "SCLK" LOC = P1 |IOSTANDARD = LVCMOS33; |
|
| 8 |
|
|
| 9 |
NET "CLK100MHz" TNM_NET = CLK100MHz; |
|
| 10 |
TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%; |
|
| 11 |
|
|
| 12 |
NET "EXT_CLOCK" TNM_NET = EXT_CLOCK; |
|
| 13 |
TIMESPEC TS_EXT_CLOCK = PERIOD "EXT_CLOCK" 4.5 ns HIGH 50%; |
|
| 14 |
|
|
| 15 |
#NET "SCLK" TNM_NET = SCLK; |
|
| 16 |
#TIMESPEC TS_SCLK = PERIOD "SCLK" 50 MHz HIGH 10%; |
|
| 17 |
NET "B<0>" CLOCK_DEDICATED_ROUTE = FALSE; |
|
| 18 |
|
|
| 19 |
# For DCM connection across the whole chip |
|
| 20 |
NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE; |
|
| 21 |
NET "PS2_CLK2" CLOCK_DEDICATED_ROUTE = FALSE; |
|
| 22 |
|
|
| 23 |
# Mode signals |
|
| 24 |
NET "M[0]" LOC = P38 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 25 |
NET "M[1]" LOC = P37 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M1 and M2 for boot from external SPI Flash Memory |
|
| 26 |
NET "M[2]" LOC = P39 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M2 for boot from internal Flash memory |
|
| 27 |
# SPI Flash Vendor Mode Select (for external SPI boot Flash) |
|
| 28 |
NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 29 |
NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 30 |
NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 31 |
|
|
| 32 |
# DIP Switches (positive signals with pull-down) |
|
| 33 |
NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 34 |
NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 35 |
NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 36 |
NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 37 |
NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 38 |
NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 39 |
NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 40 |
NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 41 |
|
|
| 42 |
# Push Buttons (positive signals with pull-down) |
|
| 43 |
NET "PB[0]" LOC = P121 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 44 |
NET "PB[1]" LOC = P120 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 45 |
NET "PB[2]" LOC = P117 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 46 |
NET "PB[3]" LOC = P116 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 47 |
|
|
| 48 |
# LED String (positive output signals) |
|
| 49 |
NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33; |
|
| 50 |
NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33; |
|
| 51 |
NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33; |
|
| 52 |
NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33; |
|
| 53 |
NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33; |
|
| 54 |
NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33; |
|
| 55 |
NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33; |
|
| 56 |
NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33; |
|
| 57 |
|
|
| 58 |
# LED Display Output Signals (negative, multiplexed) |
|
| 59 |
NET "LD_A_n" LOC = P15 |IOSTANDARD = LVCMOS33; |
|
| 60 |
NET "LD_B_n" LOC = P30 |IOSTANDARD = LVCMOS33; |
|
| 61 |
NET "LD_C_n" LOC = P21 |IOSTANDARD = LVCMOS33; |
|
| 62 |
NET "LD_D_n" LOC = P19 |IOSTANDARD = LVCMOS33; |
|
| 63 |
NET "LD_E_n" LOC = P18 |IOSTANDARD = LVCMOS33; |
|
| 64 |
NET "LD_F_n" LOC = P16 |IOSTANDARD = LVCMOS33; |
|
| 65 |
NET "LD_G_n" LOC = P24 |IOSTANDARD = LVCMOS33; |
|
| 66 |
NET "LD_DP_n" LOC = P20 |IOSTANDARD = LVCMOS33; |
|
| 67 |
|
|
| 68 |
NET "LD_0_n" LOC = P25 |IOSTANDARD = LVCMOS33; |
|
| 69 |
NET "LD_1_n" LOC = P31 |IOSTANDARD = LVCMOS33; |
|
| 70 |
NET "LD_2_n" LOC = P32 |IOSTANDARD = LVCMOS33; |
|
| 71 |
NET "LD_3_n" LOC = P13 |IOSTANDARD = LVCMOS33; # !!! Connect U1.13 with U1.33 |
|
| 72 |
NET "LD_4_n" LOC = P27 |IOSTANDARD = LVCMOS33; |
|
| 73 |
NET "LD_5_n" LOC = P29 |IOSTANDARD = LVCMOS33; |
|
| 74 |
NET "LD_6_n" LOC = P28 |IOSTANDARD = LVCMOS33; |
|
| 75 |
NET "LD_7_n" LOC = P12 |IOSTANDARD = LVCMOS33; # !!! Connect U1.12 with U1.35 |
|
| 76 |
# VGA Analog Display Connection (outputs) |
|
| 77 |
NET "VGA_R[0]" LOC = P3 |IOSTANDARD = LVCMOS33; |
|
| 78 |
NET "VGA_R[1]" LOC = P4 |IOSTANDARD = LVCMOS33; |
|
| 79 |
NET "VGA_G[0]" LOC = P5 |IOSTANDARD = LVCMOS33; |
|
| 80 |
NET "VGA_G[1]" LOC = P6 |IOSTANDARD = LVCMOS33; |
|
| 81 |
NET "VGA_B[0]" LOC = P7 |IOSTANDARD = LVCMOS33; |
|
| 82 |
NET "VGA_B[1]" LOC = P8 |IOSTANDARD = LVCMOS33; |
|
| 83 |
NET "VGA_VS" LOC = P10 |IOSTANDARD = LVCMOS33; |
|
| 84 |
NET "VGA_HS" LOC = P11 |IOSTANDARD = LVCMOS33; |
|
| 85 |
|
|
| 86 |
# Bank 1 Port (input for tests, pull-up) |
|
| 87 |
NET "B[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 88 |
NET "B[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 89 |
NET "B[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 90 |
NET "B[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 91 |
NET "B[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 92 |
NET "B[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 93 |
NET "B[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 94 |
NET "B[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 95 |
NET "B[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 96 |
NET "B[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 97 |
NET "B[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 98 |
NET "B[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 99 |
NET "B[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 100 |
NET "B[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 101 |
NET "B[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 102 |
NET "B[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 103 |
NET "B[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 104 |
NET "B[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 105 |
NET "B[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 106 |
NET "B[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 107 |
NET "B[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 108 |
NET "B[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 109 |
NET "B[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 110 |
NET "B[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 111 |
NET "B[24]" LOC = P97 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Connected with B[23] on PCB |
|
| 112 |
# PS/2 Bidirectional Port (open collector, J31 and J32) |
|
| 113 |
#NET "PS2_CLK1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # S3AN01A PCB Design has bug so these pins |
|
| 114 |
#NET "PS2_DATA1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # will be assinged after PCB redesign |
|
| 115 |
NET "PS2_CLK2" LOC = P42 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 116 |
NET "PS2_DATA2" LOC = P58 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 117 |
|
|
| 118 |
# Diferencial Signals on 4 pin header (J7) |
|
| 119 |
NET "DIF1P" LOC = P110 |IOSTANDARD = LVCMOS33 ; |
|
| 120 |
NET "DIF1N" LOC = P111 |IOSTANDARD = LVCMOS33 ; |
|
| 121 |
NET "DIF2P" LOC = P112 |IOSTANDARD = LVCMOS33 ; |
|
| 122 |
NET "DIF2N" LOC = P113 |IOSTANDARD = LVCMOS33 ; |
|
| 123 |
|
|
| 124 |
# I2C Signals (on connector J30) |
|
| 125 |
NET "I2C_SCL" LOC = P115 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 126 |
NET "I2C_SDA" LOC = P114 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 127 |
|
|
| 128 |
# Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
|
| 129 |
NET "SD1AP" LOC = P54 |IOSTANDARD = LVPECL_33; |
|
| 130 |
NET "SD1AN" LOC = P55 |IOSTANDARD = LVPECL_33; |
|
| 131 |
NET "SD1BP" LOC = P59 |IOSTANDARD = LVCMOS33 ; |
|
| 132 |
NET "SD1BN" LOC = P57 |IOSTANDARD = LVCMOS33 ; |
|
| 133 |
NET "SD2AP" LOC = P124 |IOSTANDARD = LVDS_33 ; |
|
| 134 |
NET "SD2AN" LOC = P126 |IOSTANDARD = LVDS_33 ; |
|
| 135 |
NET "SD2BP" LOC = P131 |IOSTANDARD = LVCMOS33 ; |
|
| 136 |
NET "SD2BN" LOC = P129 |IOSTANDARD = LVCMOS33 ; |
|
| 137 |
|
|
| 138 |
# SPI Memory Interface |
|
| 139 |
NET "SPI_CS_n" LOC = P41 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 140 |
NET "SPI_DO" LOC = P71 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 141 |
NET "SPI_DI" LOC = P62 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 142 |
NET "SPI_CLK" LOC = P72 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 143 |
NET "SPI_WP_n" LOC = P70 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
|
| 144 |
|
|
| 145 |
# Analog In Out |
|
| 146 |
NET "ANA_OUTD" LOC = P67 |IOSTANDARD = LVCMOS33; |
|
| 147 |
NET "ANA_REFD" LOC = P68 |IOSTANDARD = LVCMOS33; |
|
| 148 |
NET "ANA_IND" LOC = P69 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
|
| 149 |
|
|
| 150 |
/* |
|
| 151 |
# Used Signals (test points) |
|
| 152 |
NET "TPS1" LOC = P53 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
|
| 153 |
NET "TPS2" LOC = P125 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
|
| 154 |
NET "TPS3" LOC = P127 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
|
| 155 |
NET "TPS4" LOC = P130 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
|
| 156 |
NET "TPS5" LOC = P141 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
|
| 157 |
NET "TPS6" LOC = P123 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
|
| 158 |
NET "XXX1" LOC = P33 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only |
|
| 159 |
NET "XXX2" LOC = P35 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only |
|
| 160 |
*/ |
|
| Designs/Measuring_instruments/RMDS01A/HDL/gtime/src/gtime.vhd | ||
|---|---|---|
| 1 |
---------------------------------------------------------------------------------- |
|
| 2 |
-- Company: www.mlab.cz |
|
| 3 |
-- Based on code written by MIHO. |
|
| 4 |
-- |
|
| 5 |
-- HW Design Name: S3AN01A |
|
| 6 |
-- Project Name: gtime |
|
| 7 |
-- Target Devices: XC3S50AN-4 |
|
| 8 |
-- Tool versions: ISE 13.3 |
|
| 9 |
-- Description: Time and frequency synchronisation for RDMS01A. |
|
| 10 |
-- |
|
| 11 |
-- Dependencies: CLKGEN01B, GPS01A, STM32F10xRxT01A |
|
| 12 |
-- |
|
| 13 |
-- Version: $Id$ |
|
| 14 |
-- |
|
| 15 |
---------------------------------------------------------------------------------- |
|
| 16 |
|
|
| 17 |
library IEEE; |
|
| 18 |
use IEEE.STD_LOGIC_1164.ALL; |
|
| 19 |
use IEEE.numeric_std.ALL; |
|
| 20 |
|
|
| 21 |
library UNISIM; |
|
| 22 |
use UNISIM.vcomponents.all; |
|
| 23 |
|
|
| 24 |
entity gtime is |
|
| 25 |
generic ( |
|
| 26 |
-- Top Value for 100MHz Clock Counter |
|
| 27 |
MAXCOUNT: integer := 10_000; -- Maximum for the first counter |
|
| 28 |
MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
|
| 29 |
); |
|
| 30 |
port ( |
|
| 31 |
-- Clock on PCB |
|
| 32 |
CLK100MHz: in std_logic; |
|
| 33 |
|
|
| 34 |
-- Mode Signals (usualy not used) |
|
| 35 |
M: in std_logic_vector(2 downto 0); |
|
| 36 |
VS: in std_logic_vector(2 downto 0); |
|
| 37 |
|
|
| 38 |
-- Dipswitch Inputs |
|
| 39 |
DIPSW: in std_logic_vector(7 downto 0); |
|
| 40 |
|
|
| 41 |
-- Push Buttons |
|
| 42 |
PB: in std_logic_vector(3 downto 0); |
|
| 43 |
|
|
| 44 |
-- LED Bar Outputs |
|
| 45 |
LED: out std_logic_vector(7 downto 0); |
|
| 46 |
|
|
| 47 |
-- LED Display (8 digit with 7 segments and ddecimal point) |
|
| 48 |
LD_A_n: out std_logic; |
|
| 49 |
LD_B_n: out std_logic; |
|
| 50 |
LD_C_n: out std_logic; |
|
| 51 |
LD_D_n: out std_logic; |
|
| 52 |
LD_E_n: out std_logic; |
|
| 53 |
LD_F_n: out std_logic; |
|
| 54 |
LD_G_n: out std_logic; |
|
| 55 |
LD_DP_n: out std_logic; |
|
| 56 |
LD_0_n: out std_logic; |
|
| 57 |
LD_1_n: out std_logic; |
|
| 58 |
LD_2_n: out std_logic; |
|
| 59 |
LD_3_n: out std_logic; |
|
| 60 |
LD_4_n: out std_logic; |
|
| 61 |
LD_5_n: out std_logic; |
|
| 62 |
LD_6_n: out std_logic; |
|
| 63 |
LD_7_n: out std_logic; |
|
| 64 |
|
|
| 65 |
-- VGA Video Out Port |
|
| 66 |
VGA_R: out std_logic_vector(1 downto 0); |
|
| 67 |
VGA_G: out std_logic_vector(1 downto 0); |
|
| 68 |
VGA_B: out std_logic_vector(1 downto 0); |
|
| 69 |
VGA_VS: out std_logic; |
|
| 70 |
VGA_HS: out std_logic; |
|
| 71 |
|
|
| 72 |
-- Bank 1 Pins - Inputs for this Test |
|
| 73 |
B: inout std_logic_vector(24 downto 0); |
|
| 74 |
|
|
| 75 |
-- PS/2 Bidirectional Port (open collector, J31 and J32) |
|
| 76 |
PS2_CLK1: inout std_logic; |
|
| 77 |
PS2_DATA1: inout std_logic; |
|
| 78 |
PS2_CLK2: inout std_logic; |
|
| 79 |
PS2_DATA2: inout std_logic; |
|
| 80 |
|
|
| 81 |
-- Diferencial Signals on 4 pin header (J7) |
|
| 82 |
DIF1P: inout std_logic; |
|
| 83 |
DIF1N: inout std_logic; |
|
| 84 |
DIF2P: inout std_logic; |
|
| 85 |
DIF2N: inout std_logic; |
|
| 86 |
|
|
| 87 |
|
|
| 88 |
-- I2C Signals (on connector J30) |
|
| 89 |
I2C_SCL: inout std_logic; |
|
| 90 |
I2C_SDA: inout std_logic; |
|
| 91 |
|
|
| 92 |
-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
|
| 93 |
SD1AP: inout std_logic; |
|
| 94 |
SD1AN: inout std_logic; |
|
| 95 |
SD1BP: inout std_logic; |
|
| 96 |
SD1BN: inout std_logic; |
|
| 97 |
SD2AP: inout std_logic; |
|
| 98 |
SD2AN: inout std_logic; |
|
| 99 |
SD2BP: inout std_logic; |
|
| 100 |
SD2BN: inout std_logic; |
|
| 101 |
|
|
| 102 |
-- Analog In Out |
|
| 103 |
ANA_OUTD: out std_logic; |
|
| 104 |
ANA_REFD: out std_logic; |
|
| 105 |
ANA_IND: in std_logic; |
|
| 106 |
|
|
| 107 |
-- SPI Memory Interface |
|
| 108 |
SPI_CS_n: inout std_logic; |
|
| 109 |
SPI_DO: inout std_logic; |
|
| 110 |
SPI_DI: inout std_logic; |
|
| 111 |
SPI_CLK: inout std_logic; |
|
| 112 |
SPI_WP_n: inout std_logic |
|
| 113 |
); |
|
| 114 |
end entity gtime; |
|
| 115 |
|
|
| 116 |
|
|
| 117 |
architecture gtime_a of gtime is |
|
| 118 |
|
|
| 119 |
|
|
| 120 |
-- Counter |
|
| 121 |
-- ---------------- |
|
| 122 |
|
|
| 123 |
signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter 2 Hz (binary) |
|
| 124 |
|
|
| 125 |
|
|
| 126 |
-- LED Display |
|
| 127 |
-- ----------- |
|
| 128 |
|
|
| 129 |
signal Number: std_logic_vector(31 downto 0) := X"00000000"; -- LED Display Input |
|
| 130 |
signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency |
|
| 131 |
signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
|
| 132 |
signal Enable: std_logic; |
|
| 133 |
signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
|
| 134 |
signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
|
| 135 |
signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
|
| 136 |
|
|
| 137 |
|
|
| 138 |
-- signal LO_CLOCK: std_logic; -- Frequency divided by 2 |
|
| 139 |
signal EXT_CLOCK: std_logic; -- Input Frequency |
|
| 140 |
|
|
| 141 |
signal Decko: std_logic; -- D flip-flop |
|
| 142 |
signal State: unsigned(2 downto 0) := (others => '0'); -- Inner states of automata |
|
| 143 |
|
|
| 144 |
signal SCLK: std_logic; |
|
| 145 |
signal SCLK2: std_logic; |
|
| 146 |
|
|
| 147 |
|
|
| 148 |
begin |
|
| 149 |
|
|
| 150 |
-- Counter |
|
| 151 |
process (EXT_CLOCK) |
|
| 152 |
begin |
|
| 153 |
|
|
| 154 |
if rising_edge(EXT_CLOCK) then |
|
| 155 |
|
|
| 156 |
if (State = 2) or (State = 0) then |
|
| 157 |
Counter <= Counter + 1; |
|
| 158 |
end if; |
|
| 159 |
if (State = 1) then |
|
| 160 |
Freq(31 downto 0) <= std_logic_vector(Counter); |
|
| 161 |
Counter <= (others => '0'); |
|
| 162 |
end if; |
|
| 163 |
end if; |
|
| 164 |
|
|
| 165 |
end process; |
|
| 166 |
|
|
| 167 |
|
|
| 168 |
-- Sampling 1PPS signal |
|
| 169 |
process (EXT_CLOCK) |
|
| 170 |
begin |
|
| 171 |
if rising_edge(EXT_CLOCK) then |
|
| 172 |
Decko <= B(22); |
|
| 173 |
end if; |
|
| 174 |
end process; |
|
| 175 |
|
|
| 176 |
-- Automata for controlling the Counter |
|
| 177 |
process (EXT_CLOCK) |
|
| 178 |
begin |
|
| 179 |
if rising_edge(EXT_CLOCK) then |
|
| 180 |
if (Decko = '1') then |
|
| 181 |
if (State < 2) then |
|
| 182 |
State <= State + 1; |
|
| 183 |
end if; |
|
| 184 |
else |
|
| 185 |
State <= (others => '0'); |
|
| 186 |
end if; |
|
| 187 |
end if; |
|
| 188 |
end process; |
|
| 189 |
|
|
| 190 |
process (Decko) |
|
| 191 |
begin |
|
| 192 |
if Decko = '0' then |
|
| 193 |
LED(6) <= '1'; |
|
| 194 |
else |
|
| 195 |
LED(6) <= '0'; |
|
| 196 |
end if; |
|
| 197 |
end process; |
|
| 198 |
|
|
| 199 |
SCLK <= B(0); |
|
| 200 |
|
|
| 201 |
-- Output Shift Register |
|
| 202 |
process (Decko,SCLK) |
|
| 203 |
begin |
|
| 204 |
if (Decko = '0') then |
|
| 205 |
Number(31 downto 0) <= Freq(31 downto 0); |
|
| 206 |
else |
|
| 207 |
if rising_edge(SCLK) then |
|
| 208 |
Number(30 downto 0) <= Number(31 downto 1); |
|
| 209 |
end if; |
|
| 210 |
end if; |
|
| 211 |
end process; |
|
| 212 |
|
|
| 213 |
B(1) <= Number(0); |
|
| 214 |
B(2) <= Decko; |
|
| 215 |
|
|
| 216 |
LED(7) <= Decko; -- Display 1PPS pulse on LEDbar |
|
| 217 |
LED(5 downto 0) <= (others => '0'); |
|
| 218 |
|
|
| 219 |
-- LED Display (multiplexed) |
|
| 220 |
-- ========================= |
|
| 221 |
|
|
| 222 |
-- Connect LED Display Output Ports (negative outputs) |
|
| 223 |
LD_A_n <= not (Segments(0) and Enable); |
|
| 224 |
LD_B_n <= not (Segments(1) and Enable); |
|
| 225 |
LD_C_n <= not (Segments(2) and Enable); |
|
| 226 |
LD_D_n <= not (Segments(3) and Enable); |
|
| 227 |
LD_E_n <= not (Segments(4) and Enable); |
|
| 228 |
LD_F_n <= not (Segments(5) and Enable); |
|
| 229 |
LD_G_n <= not (Segments(6) and Enable); |
|
| 230 |
LD_DP_n <= not (Segments(7) and Enable); |
|
| 231 |
|
|
| 232 |
LD_0_n <= not Digits(0); |
|
| 233 |
LD_1_n <= not Digits(1); |
|
| 234 |
LD_2_n <= not Digits(2); |
|
| 235 |
LD_3_n <= not Digits(3); |
|
| 236 |
LD_4_n <= not Digits(4); |
|
| 237 |
LD_5_n <= not Digits(5); |
|
| 238 |
LD_6_n <= not Digits(6); |
|
| 239 |
LD_7_n <= not Digits(7); |
|
| 240 |
|
|
| 241 |
-- Time Multiplex |
|
| 242 |
process (CLK100MHz) |
|
| 243 |
begin |
|
| 244 |
if rising_edge(CLK100MHz) then |
|
| 245 |
if MuxCounter < MUXCOUNT-1 then |
|
| 246 |
MuxCounter <= MuxCounter + 1; |
|
| 247 |
else |
|
| 248 |
MuxCounter <= (others => '0'); |
|
| 249 |
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left |
|
| 250 |
Enable <= '0'; |
|
| 251 |
end if; |
|
| 252 |
if MuxCounter > (MUXCOUNT-4) then |
|
| 253 |
Enable <= '1'; |
|
| 254 |
end if; |
|
| 255 |
end if; |
|
| 256 |
end process; |
|
| 257 |
|
|
| 258 |
-- HEX to 7 Segmet Decoder |
|
| 259 |
-- -- A |
|
| 260 |
-- | | F B |
|
| 261 |
-- -- G |
|
| 262 |
-- | | E C |
|
| 263 |
-- -- D H |
|
| 264 |
-- ABCDEFGH |
|
| 265 |
Segments <= "11111100" when Code="0000" else -- Digit 0 |
|
| 266 |
"01100000" when Code="0001" else -- Digit 1 |
|
| 267 |
"11011010" when Code="0010" else -- Digit 2 |
|
| 268 |
"11110010" when Code="0011" else -- Digit 3 |
|
| 269 |
"01100110" when Code="0100" else -- Digit 4 |
|
| 270 |
"10110110" when Code="0101" else -- Digit 5 |
|
| 271 |
"10111110" when Code="0110" else -- Digit 6 |
|
| 272 |
"11100000" when Code="0111" else -- Digit 7 |
|
| 273 |
"11111110" when Code="1000" else -- Digit 8 |
|
| 274 |
"11110110" when Code="1001" else -- Digit 9 |
|
| 275 |
"11101110" when Code="1010" else -- Digit A |
|
| 276 |
"00111110" when Code="1011" else -- Digit b |
|
| 277 |
"10011100" when Code="1100" else -- Digit C |
|
| 278 |
"01111010" when Code="1101" else -- Digit d |
|
| 279 |
"10011110" when Code="1110" else -- Digit E |
|
| 280 |
"10001110" when Code="1111" else -- Digit F |
|
| 281 |
"00000000"; |
|
| 282 |
|
|
| 283 |
Code <= Number( 3 downto 0) when Digits="00000001" else |
|
| 284 |
Number( 7 downto 4) when Digits="00000010" else |
|
| 285 |
Number(11 downto 8) when Digits="00000100" else |
|
| 286 |
Number(15 downto 12) when Digits="00001000" else |
|
| 287 |
Number(19 downto 16) when Digits="00010000" else |
|
| 288 |
Number(23 downto 20) when Digits="00100000" else |
|
| 289 |
Number(27 downto 24) when Digits="01000000" else |
|
| 290 |
Number(31 downto 28) when Digits="10000000" else |
|
| 291 |
"0000"; |
|
| 292 |
|
|
| 293 |
|
|
| 294 |
-- Diferencial In/Outs |
|
| 295 |
-- ======================== |
|
| 296 |
DIFbuffer1 : IBUFGDS |
|
| 297 |
generic map ( |
|
| 298 |
DIFF_TERM => FALSE, -- Differential Termination |
|
| 299 |
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, |
|
| 300 |
-- "0"-"16" |
|
| 301 |
IOSTANDARD => "LVPECL_33") |
|
| 302 |
port map ( |
|
| 303 |
I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |
|
| 304 |
IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) |
|
| 305 |
O => EXT_CLOCK -- Buffer output - Counter INPUT |
|
| 306 |
); |
|
| 307 |
|
|
| 308 |
OBUFDS_inst : OBUFDS |
|
| 309 |
generic map ( |
|
| 310 |
IOSTANDARD => "LVDS_33") |
|
| 311 |
port map ( |
|
| 312 |
O => SD2AP, -- Diff_p output (connect directly to top-level port) |
|
| 313 |
OB => SD2AN, -- Diff_n output (connect directly to top-level port) |
|
| 314 |
I => EXT_CLOCK -- Buffer input are connected directly to IBUFGDS |
|
| 315 |
); |
|
| 316 |
|
|
| 317 |
-- Output Signal on SATA Connector |
|
| 318 |
-- SD1AP <= 'Z'; -- Counter INPUT |
|
| 319 |
-- SD1AN <= 'Z'; |
|
| 320 |
SD1BP <= 'Z'; |
|
| 321 |
SD1BN <= 'Z'; |
|
| 322 |
|
|
| 323 |
-- Input Here via SATA Cable |
|
| 324 |
-- SD2AP <= 'Z'; -- Counter OUTPUT |
|
| 325 |
-- SD2AN <= 'Z'; |
|
| 326 |
SD2BP <= 'Z'; |
|
| 327 |
SD2BN <= 'Z'; |
|
| 328 |
|
|
| 329 |
|
|
| 330 |
-- Unused Signals |
|
| 331 |
-- ============== |
|
| 332 |
|
|
| 333 |
-- Differential inputs onn header |
|
| 334 |
DIF1N <= 'Z'; |
|
| 335 |
DIF1P <= 'Z'; |
|
| 336 |
DIF2N <= 'Z'; |
|
| 337 |
DIF2P <= 'Z'; |
|
| 338 |
|
|
| 339 |
-- I2C Signals (on connector J30) |
|
| 340 |
I2C_SCL <= 'Z'; |
|
| 341 |
I2C_SDA <= 'Z'; |
|
| 342 |
|
|
| 343 |
-- SPI Memory Interface |
|
| 344 |
SPI_CS_n <= 'Z'; |
|
| 345 |
SPI_DO <= 'Z'; |
|
| 346 |
SPI_DI <= 'Z'; |
|
| 347 |
SPI_CLK <= 'Z'; |
|
| 348 |
SPI_WP_n <= 'Z'; |
|