o: ActiveSupport::Cache::Entry :@compressedF:@value""
| Modules/CPLD_FPGA/S6AN01A/PrjInfo.txt | ||
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| 1 |
[InfoShortDescription.en] |
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| 2 |
Xilinx Spartan 6 XC6SLX9T FPGA Developing Board |
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| 3 |
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| 4 |
[InfoShortDescription.cs] |
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| 5 |
Vývojový modul s FPGA Xilinx Spartan 6 XC6SLX9T |
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| 6 |
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| 7 |
[InfoLongDescription.en] |
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| 8 |
FPGA development module for basic signal and data processing. This breakout board differs from other constructions by high number of differential pairs take out to LVDS or LVPECL connectors. |
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| 9 |
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| 10 |
[InfoLongDescription.cs] |
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| 11 |
FPGA vývojová deska pro základní zpracování signálů. Od běžných vývojových desek se odlišuje hlavně zvýšeným množstvím diferenčňích kanálů vyvedených na konektory. |
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| 12 |
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| 13 |
[End] |
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| Modules/CPLD_FPGA/S6AN01A/CAM_PROFI/Preview.gvp | ||
|---|---|---|
| 1 |
(gerbv-file-version! "2.0A") |
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| 2 |
(define-layer! 5 (cons 'filename "V2.PHO")(cons 'visible #f)(cons 'color #(53713 6939 26728))) |
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| 3 |
(define-layer! 4 (cons 'filename "V1.PHO")(cons 'visible #t)(cons 'color #(54741 65021 13107))) |
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| 4 |
(define-layer! 3 (cons 'filename "T1.PHO")(cons 'visible #t)(cons 'color #(0 50115 50115))) |
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| 5 |
(define-layer! 2 (cons 'filename "M2.PHO")(cons 'visible #f)(cons 'color #(30069 62194 26471))) |
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| 6 |
(define-layer! 1 (cons 'filename "M1.PHO")(cons 'visible #t)(cons 'color #(49601 0 57568))) |
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| 7 |
(define-layer! 0 (cons 'filename "BOARD.PHO")(cons 'visible #t)(cons 'color #(29555 29555 57054))) |
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| 8 |
(define-layer! -1 (cons 'filename "./")(cons 'visible #f)(cons 'color #(0 0 0))) |
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| 9 |
(set-render-type! 3) |
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